Method and apparatus for phase aligning two clock signals utilizing a programmable phase adjustment circuit

A method comprising:

• receiving a first measured phase difference between a first clock signal and a second clock signal;
• comparing the first measured phase difference to a maximum allowable first phase difference value;
• adding a first phase adjustment to the first clock signal if the measured phase difference is greater than the maximum allowable first phase difference value and;
• selecting the first clock signal as an active clock after the measured phase difference is not greater than the maximum allowable first phase difference value.

A computer readable medium comprising a set of instructions for enabling a system to:

• receive a first measured phase difference between a first clock signal and a second clock signal;
• compare the first measured phase difference to a maximum allowable first phase difference value;
• add a first phase adjustment to the first clock signal if the measured phase difference is greater than the maximum allowable first phase difference value;
• repeat receiving the first measured phase difference, comparing the first measured phase difference and adding the first phase adjustment until the measured phase difference is not greater than the maximum allowable first phase difference value;
• and
• select the first clock signal as an active clock after the measured phase difference is not greater than the maximum allowable first phase difference value.

An apparatus comprising:

• reporting circuit configured to receive a measured phase difference between a first clock signal and a second clock signal, wherein the reporting circuit comprises a notification circuit configured to notify a processor of a completion of measuring the phase difference between the first clock signal and the second clock signal;
• selection circuit configured to select a configurable phase adjustment according to the measured phase difference;
• and
• granularity adjustment circuit configured to add the configurable phase adjustment to the first clock signal generating a phase adjusted clock signal.

An apparatus comprising:

• receiving means for receiving a first measured phase difference between a first clock signal and a second clock signal;
• comparing means for comparing the first measured phase difference to a maximum allowable first phase difference value;
• adding means for adding a first phase adjustment to the first clock signal if the measured phase difference is greater than the maximum allowable first phase difference value;
• and
• selecting means for selecting the first clock signal as an active clock after the measured phase difference is not greater than the maximum allowable first phase difference value.