US 6,549,045 B1 · Circuit for providing clock signals with low skew

Abstract

A digital, preferably programmable, circuit is disclosed for providing one or more clock signals with variable frequency and/or phase. The clock signals exhibit a low amount of skew relative to other clock signals and data signals provided by the circuit. In one embodiment, the circuit includes a plurality of channels each having a parallel-in/serial-out shift register, a flip-flop, and a delay circuit. The shift register can receive data bits in data channels or clock frequency select bits in frequency-divided clock channels. The serial output from the register acts as an input for the flip flop, both of which are triggered by an input reference clock. The delay circuit delays the input reference clock. In each channel, a multiplexer is configured to select the clock or data channel output from the register, flip-flop, and delay circuit outputs. Since the delays in all output paths are matched, skew is minimized.

Claims31

Dependent claims

A circuit comprising a plurality of channel circuits, each channel circuit including:

a shift register circuit for receiving a plurality of input bit signals in parallel and shifting out a serial register output signal in response, the shift register circuit being triggered by an input clock signal;
a flip-flop circuit for receiving the register output signal at an input thereof and providing a flip-flop output signal in response, the flip-flop circuit being triggered by the input clock signal;
and
a multiplexer circuit for receiving the register output signal and the flip-flop output signal at first and second inputs thereof, the multiplexer circuit being configurable to output the signal at one of the multiplexer inputs as a channel output signal.

1 more element

A circuit comprising a plurality of channel circuits, each channel circuit comprising:

a shift register circuit for receiving a plurality of input bit signals in parallel and shifting out a serial register output signal in response, the shift register circuit being triggered by an input clock signal;
a flip-flop circuit for receiving the register output signal at an input thereof and providing a flip-flop output signal in response, the flip-flop circuit being triggered by the input clock signal;
a delay circuit for receiving the input clock signal and outputting a delayed version of the input clock signal;
and
a multiplexer circuit for receiving the register output signal, the flip-flop output signal and the delayed version of the input clock signal at first, second and third inputs thereof, the multiplexer circuit being configurable to output the signal at one of the first, second and third multiplexer inputs as a channel output signal.

2 more elements

A circuit for providing a clock signal comprising:

a shift register circuit for receiving a plurality of fixed clock frequency select bit signals in parallel and shifting out a register output clock signal in response, the shift register circuit being triggered by an input clock signal such that the register output clock signal has a frequency that is divided down by a factor of at least two with respect to the input clock signal;
a flip-flop circuit for receiving the register output clock signal at an input thereof and providing a flip-flop output clock signal in response, the flip-flop circuit being triggered by the input clock signal and the flip-flop output clock signal having the same frequency as the register output clock signal;
and
a multiplexer circuit for receiving the register output c lock signal and the flip-flop output clock signal at first and second multiplexer inputs thereof, the multiplexer circuit being configurable to output the signal at one of the multiplexer inputs as a clock output signal.

1 more element

Dependencies are inferred from the claim text.

Circuit for providing clock signals with low skew

Life of this patent

Circuit for providing clock signals with low skew

Life of this patent

Abstract

Claims31