US 6,549,042 B2 · Complementary data line driver circuits with conditional charge recycling capability that may be used in random access and content addressable memory devices and method of operating same

Abstract

Complementary data line driver circuits conserve power by evaluating data on complementary data lines and providing conditional charge recycling in the event the new data to be provided to the complementary data lines differs from the old data residing thereon. These devices and circuits include first and second data lines within a complementary data line pair and a driver control circuit that is electrically coupled to the data line pair. The driver control circuit compares the old data on the data line pair against new data to be provided to the data line pair. Based on the comparison and determination that the old data is opposite the new data, the driver control circuit switches the old data to the new data in two steps. The first of the two steps includes transferring charge from the more positively biased one of the first and second data lines to the other data line in the data line pair, preferably for a duration sufficient to substantially equilibrate voltages on the first and second data lines.

Claims46

Dependent claims

A complementary data line driver circuit, comprising:

first and second data lines within a complementary data line pair;
and
a driver control circuit that is electrically coupled to said data line pair and is configured to perform an evaluation of old data on said data line pair relative to new data to be provided to said data line pair and is further configured to response to the evaluation by switching the old data to the new data when the new data is opposite the old data by first transferring charge from a more positively biased one of said first and second data lines to the other data line in said data line pair and then driving the first and second data lines with the new data.

A complementary data line driver circuit, comprising:

first and second data lines within a complementary data line pair;
a true data line driver device comprising a first PMOS transistor and first NMOS transistor arranged as a totem pole between a power supply line and a reference line and connected together at a first output that is electrically connected to the first data line;
a complementary data line driver device comprising a second PMOS transistor and second NMOS transistor arranged as a totem pole between the power supply line and the reference line and connected together at a second output that is electrically connected to the second data line;
an equalization transistor having a first current carrying terminal electrically coupled to said first data line and a second current carrying terminal electrically coupled to said second data line;
and
a control circuit that in response to complementary signals DATA and DATAB that represent new data to be provided to said data line pair, switches old data on said data line pair to the new data by:
driving a gate of the first PMOS transistor with a signal equal to DATAB+QB;
driving a gate of the second PMOS transistor with a signal equal to DATA+Q;
driving a gate of the first NMOS transistor with a signal equal to DATAB×QB;
driving a gate of the second NMOS transistor with a signal equal to DATA×Q;
and
driving a gate of said equalization transistor with a signal equal to (DATA⊕Q),
where Q and QB are complementary signals that represent the old data, + designates an OR operator, × designates a AND operator and ⊕ designates an exclusive OR operator.

10 more elements

Dependencies are inferred from the claim text.

Complementary data line driver circuits with conditional charge recycling capability that may be used in random access and content addressable memory devices and method of operating same

Life of this patent

Complementary data line driver circuits with conditional charge recycling capability that may be used in random access and content addressable memory devices and method of operating same

Life of this patent

Abstract

Claims46