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US 6,549,041 B2Granted
Scheme for delay locked loop reset protection
AssigneeMicron Technology, Inc.
InventorWilliam C. Waldrop
Life of this patent
Estimating the term…
Abstract
Systems and methods are provided for operating a delay locked loop during a reset. The systems and methods provide for activating a reset mode signal to prevent a phase lock signal from forcing the DLL out of a reset, and deactivating the reset mode signal only after at least one shifting operation is performed to allow the phase lock signal to correctly allow the DLL to be out of the reset.
Claims36
A circuit comprising:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for disabling the shifting operation when the external and internal signals are synchronized;
- a reset unit for resetting the shift register in a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
5 more elements
A circuit comprising:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for determining a delay between the external and internal signals;
- a reset unit for resetting the shift register in a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
5 more elements
A circuit comprising:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate;
- a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
5 more elements
An integrated circuit comprising:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- and
- a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for disabling the shifting operation when the external and internal signals are synchronized;
- a reset unit for resetting the shift register in a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
9 more elements
An integrated circuit comprising:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- and
- a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for determining a delay between the external and internal signals;
- a reset unit for resetting the shift register during a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
9 more elements
An integrated circuit comprising:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- and
- a delay circuit for providing timing to the output circuit to output the data to a plurality of data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate;
- a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
9 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for disabling the shifting operation when the external and internal signals are synchronized;
- a reset unit for resetting the shift register in a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
11 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for disabling the shifting operation when the external and internal signals are synchronized;
- a reset unit for resetting the shift register in a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the compare unit from disabling the shifting operation in the reset mode.
11 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for determining a delay between the external and internal signals;
- a reset unit for resetting the shift register during a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
11 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for determining a delay between the external and internal signals;
- a reset unit for resetting the shift register during a reset mode;
- and
- a false lock protection unit connected to the compare unit and the reset unit for enabling the shift register to perform at least one shifting operation during the reset mode.
11 more elements
A system comprising:
- a processor;
- and
- a dynamic memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate;
- a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
11 more elements
A system comprising:
- a processor;
- and
- a static memory device connected to the processor via a plurality of data lines, the memory device including:
- a plurality of memory cells;
- an output circuit for receiving data from the memory cells;
- a delay circuit for providing timing to the output circuit to output the data to the data lines, the delay circuit including:
- a delay line for receiving an external signal to generate an internal signal;
- a shift register connected to the delay line for performing a shifting operation to synchronize the external and internal signals;
- and
- a phase detector connected to the shift register, the phase detector including:
- a compare unit for comparing the external signal and a delayed version of the internal based on a first sampling rate;
- a reset unit for changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized;
- and
- a false lock protection unit connected to the compare unit and the reset unit for preventing the reset unit from changing the first sampling rate to the second sampling rate when the external and internal signals are not synchronized during a reset mode.
11 more elements
A method comprising:
- delaying an external signal to generate an internal signal;
- determining a delay between the external and internal signals;
- performing a shifting operation to adjust the delay;
- disabling the shifting operation when the external and internal signals are synchronized;
- activating a reset signal in a reset mode;
- performing at least one shifting operation in the reset mode.
3 more elements
A method comprising:
- delaying an external signal to generate an internal signal;
- determining a delay between the external and internal signals;
- performing a shifting operation to adjust the delay;
- disabling the shifting operation when the external and internal signals are synchronized;
- activating a reset signal in a rest mode;
- and
- preventing the disabling of the shifting operation in the reset mode.
4 more elements
A method of comprising:
- delaying an external signal to generate an internal signal;
- comparing the external and internal signals based on a first sampling rate;
- performing a shifting operation based on the comparison to synchronize the external and internal signals;
- changing the first sampling rate to a second sampling rate when the external and internal signals are synchronized;
- activating a reset signal in a reset mode;
- and
- preventing the changing of the first sampling rate to the second sampling rate when the external and internal signals are not synchronized in the reset mode.
4 more elements
Dependencies are inferred from the claim text.