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US 6,549,040 B1Granted
Leakage-tolerant keeper with dual output generation capability for deep sub-micron wide domino gates
AssigneeIntel Corporation
InventorsAtila Alvandpour, Krishnamurthy Soumyanath, Ram K. Krishnamurthy
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Abstract
A circuit including a clock signal input to receive a clock signal, at least one data signal input to receive at least one data signal, and a multiple input conditional inverter to receive the clock signal and the data signal, and to generate a dynamic output. The circuit also includes a conditional keeper circuit to charge a dynamic output node when the clock is evaluating and the dynamic output is high.
Claims24
A circuit comprising:
- a clock signal input to receive a clock signal;
- at least one data signal input to receive at least one data signal;
- a dynamic output coupled to the clock signal input and the at least one data signal input;
- and
- a conditional keeper circuit, coupled to the dynamic output, to hold a first gain rate on the dynamic output whenever the circuit is in an evaluating mode and the dynamic output is at a high logic level, and to hold a second gain rate on the dynamic output whenever the circuit is in the evaluating mode and the dynamic output is transitioning from the high logic level to a low logic level.
2 more elements
A method comprising:
- receiving an input signal;
- receiving a low clock signal to generate a dynamic output;
- driving the dynamic output to a high level at a first gain rate with a conditional keeper circuit whenever the input signal is at a low logic level;
- and
- driving the dynamic output to a high level at a second gain rate with the conditional keeper circuit whenever the input signal is at a high logic level.
2 more elements
A conditional keeper circuit comprising:
- a delay element having an input to receive a clock signal and an output;
- a NAND gate having a first input to receive the output of the delay element, a second input to receive a dynamic output node and an output;
- a first p-type transistor having a source connected to a positive supply voltage, a drain connected to the dynamic output node and a gate coupled to the output of the NAND gate;
- an inverter to coupled to the dynamic output node to invert a dynamic output signal;
- and
- a second p-type transistor including a source connected to a positive power supply voltage, a drain coupled to the dynamic output node, and a gate coupled to the output of the inverter;
- wherein the conditional keeper holds a first gain rate on the dynamic output during an evaluating mode whenever the dynamic output node is at a high logic level, and holds a second gain rate on the dynamic output node during the evaluating mode whenever the dynamic output is transitioning from the high logic level to a low logic level.
4 more elements
Dependencies are inferred from the claim text.