US 6,549,038 B1Granted

Method of high-performance CMOS design

AssigneeUniversity of Washington

InventorsCarl Sechen, Larry McMurchie, Tyler Thorp, Gin Yee

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Abstract

A method for improving the speed of conventional CMOS logic families is disclosed. When applied to static CMOS, OPL retains the restoring character of the logic family, including its high noise margins. Speedups of 2× to 3× over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families, in combination with remapping to wide-input NORs, OPL yields speedups of 4× to 5× over static CMOS. Since OPL applied to static CMOS is faster than conventional domino logic, and since it has higher noise margins than domino logic, we believe it will scale much better than domino with future processing technologies.

Claims16

Dependent claims

A method of clocking a multilevel logic circuit, each level of the multilevel logic circuit having inverting dynamic logic gates only, each inverting dynamic logic gate implementing an arbitrary inverting logic function, each inverting dynamic logic gate driving the output to the value of the logic function when triggered by a clock signal, each inverting dynamic logic gate having all inputs and an output fully pre-charged to VDD (logic “1”), the method comprising:

determining a gate optimum clock arrival time for each inverting dynamic logic gate by trying all possible gate clock arrival times and choosing the gate clock arrival time that yields a minimum delay for each inverting dynamic logic gate;
determining a level optimum clock arrival time for each level by determining the maximum clock arrival time, over all gate arrival times, for all inverting dynamic logic gates in a level;
determining a multilevel logic circuit optimum delay by sequentially determining level optimum clock arrival times for each level in the multilevel logic circuit;
applying to each inverting dynamic logic gate in a given level, a clock signal at the level optimum clock arrival time for that level.

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