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US 6,549,037 B1Granted
Apparatus and circuit having reduced leakage current and method therefor
AssigneeIntel Corporation
InventorsLawrence T. Clark, Kimberley E. Wagner
Life of this patent
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Abstract
Briefly, in accordance with one embodiment of the invention, an integrated circuit comprises a first stage that provides differential outputs in one mode and substantially equal outputs in another mode.
Claims16
An apparatus having an integrated circuit, the integrated circuit comprising;
- a first stage adapted to provide a first output voltage potential and a second output voltage potential that are substantially equal when the integrated circuit is in a first operational mode and differential when the integrated circuit is in a second operational mode, and wherein the first stage further comprises an n-channel transistor and at least two p-channel transistors having a gate terminal adapted to receive an enable signal;
- and
- a second stage coupled to the first stage and comprising at least two transistors, wherein the second stage is adapted to provide a third output voltage potential and a fourth output voltage potential that are substantially equal when the integrated circuit is in the first operational mode.
An integrated circuit comprising:
- a first stage adapted to receive at least two input signals, wherein the first stage is adapted to provide a first output signal and a second output signal, the first output signal being differential with respect to the second output signal, and wherein the first stage further comprises at least two p-channel metal oxide semiconductor (PMOS) transistors having a gate terminal adapted to receive an enable signal;
- and
- a second stage adapted to receive at least two input signals, the first output signal, and the second output signal, wherein the second stage is further adapted to provide a third output signal and a fourth output signal, and
- wherein the first output signal, the second output signal, the third output signal, and the fourth output signal are substantially equal when the integrated circuit is in a first mode for all combinations of values of the at least two input signals of the first stage and second stage.
1 more element
A method of reducing the flow of current through a first stage and a second stage of an integrated circuit, comprising:
- selectively disabling the flow of current through at least a portion of the first stage of the integrated circuit, the first stage including two p-channel transistors;
- and
- driving a pair of differential outputs of the first stage and the second stage so that a pair of differential outputs of the first stage and the second stage are substantially equal.
Dependencies are inferred from the claim text.