Circuit and method for measuring capacitance

A circuit for measuring a capacitance of a capacitive load, comprising:

• a first type-1 MOS transistor, wherein a source of the first type-1 MOS transistor is coupled to a first power source;
• a second type-1 MOS transistor, wherein a source of the second type-1 MOS transistor is coupled to a second power source, and a first input voltage is applied to the gates of the first and the second type-1 MOS transistor;
• a first type-2 MOS transistor, wherein a source of the first type-2 MOS transistor is coupled to a third power source, and the drain of the first type-2 MOS transistor is coupled to the drain of the first type-1 MOS transistor;
• a second type-2 MOS transistor, wherein a source of the second type-2 MOS transistor is coupled to the third power source, and the drain of the second type-2 MOS transistor is coupled to the drain of the second type-1 MOS transistor, and a second input voltage is applied to the gates of the first and the second type-2 MOS transistor;
• a capacitive load coupled between the drains of the first and the second type-1 MOS transistors;
• and
• a MOS transistor, coupled to the drain of the second type-1 MOS transistor.

A circuit for measuring a capacitance of a capacitive load, comprising:

• a first PMOS transistor, wherein a source of the first PMOS transistor is coupled to a power source;
• a second PMOS transistor, wherein a source of the second PMOS transistor is coupled to the power source, and a first input voltage is applied to the gates of the first and the second PMOS transistor;
• a first NMOS transistor, wherein a source of the first NMOS transistor is coupled to a ground, and the drain of the first NMOS transistor is coupled to the drain of the first type-1 MOS transistor;
• a second NMOS transistor, wherein a source of the second NMOS transistor is coupled to the ground, and the drain of the second NMOS transistor is coupled to the drain of the second PMOS transistor, and a second input voltage is applied to the gates of the first and the second NMOS transistor;
• a capacitive load coupled between the drains of the first and the second PMOS transistors;
• and
• a control element coupled to the drain of the second PMOS transistor.

A method for measuring a capacitive load, wherein the capacitive load is coupled between a first and a second nodes, and drains of a first PMOS and a first NMOS transistors are coupled to the first node, and drains of a second PMOS and a second NMOS transistors are coupled to the second node, and a pad is coupled to the second node, the method comprising steps of:

• applying a power source to sources of the first and the second PMOS transistors;
• applying a ground to sources of the first and the second NMOS transistors;
• applying a first input voltage to gates of the first and the second PMOS transistors and a second input voltage to gates of the first and the second NMOS transistors simultaneously;
• applying the ground to the pad for measuring a first output current;
• floating the pad for measuring a second output current;
• subtracting the first and the second output currents to obtain a capacitor current flowing through the capacitive load;
• and
• calculating a capacitance of the capacitive load using the capacitor current.