Mechanism for measurement of time duration between asynchronous events

A method of measuring the time duration between asynchronous events, said method comprising the steps of:

• generating a first edge event signal and an associated first clock phase signal, said first edge event signal adapted to indicate a first transition of an input data signal from a low to high state, said first clock phase signal adapted to indicate whether said first transition of said data signal occurred in a first or second half cycle of a first clock signal;
• generating a second edge event signal and an associated second clock phase signal, said second edge event signal adapted to indicate a second transition of said input data signal from a high to low state, said second clock phase signal adapted to indicate whether said second transition of said data signal occurred in a first or second half cycle of a first clock signal;
• enabling an N-bit counter in response to said first edge event signal;
• disabling said counter in response to said second edge event signal;
• and
• compensating said N-bit counter output in accordance with said first clock phase signal and said second clock phase signal so as to generate an N+1 bit output representing said time duration.

An apparatus for measuring the relative timing drift between a first clock and a slower second clock, comprising:

• means for generating a first edge event signal and an associated first clock phase signal, said first edge event signal adapted to indicate a first transition of said second clock from a low to high state, said first clock phase signal adapted to indicate whether said first transition of said second clock occurred in a first or second half cycle of said first clock;
• means for generating a second edge event signal and an associated second clock phase signal, said second edge event signal adapted to indicate a second transition of said second clock from a high to low state, said second clock phase signal adapted to indicate whether said second transition of said second clock occurred in a first or second half cycle of said first clock;
• a counter adapted to generate an N bit output wherein counting is enabled in response to said first edge event signal and wherein counting is disabled in response to said second edge event signal;
• and
• means for correcting said N-bit counter output in accordance with said first clock phase signal and said second clock phase signal so as to generate an N+1 bit output representing said time duration.

An apparatus for measuring the relative timing drift between a first clock and a slower second clock, comprising:

• a first metastability resolver clocked by said first clock for generating a first edge event signal and an associated first clock phase signal, said first edge event signal corresponding to the detection of a rising edge of said second clock, said first clock phase signal adapted to indicate whether said rising edge of said second clock occurred in a first or second half cycle of said first clock;
• a second metastability resolver clocked by an inverted first clock for generating a second edge event signal and an associated second clock phase signal, said second edge event signal corresponding to the detection of a falling edge of said second clock, said second clock phase signal adapted to indicate whether said falling edge of said second clock occurred in a first or second half cycle of said first clock;
• a counter adapted to generate an N-bit output wherein counting is enabled in response to said first edge event signal and wherein counting is disabled in response to said second edge event signal;
• a correction circuit adapted to generate a correction factor in accordance with said first clock phase signal and said second clock phase signal;
• and
• an adder adapted to add a least significant bit to said counter output to yield an N+1 bit value and to generate the sum of said correction factor and said N+1 bit value to yield said relative timing drift between said first clock and said second clock.