High speed bias voltage generating circuit
AssigneeSilicon Storage Technology, Inc.
InventorJun Li
Life of this patent
Estimating the term…
Abstract
A high speed bias voltage generating circuit 10 for use with semiconductor devices. The bias voltage generating circuit 10 includes three circuits or circuit portions 12 , 14 and 16 which cooperatively control the output voltage and current of the circuit 10. The standby circuit 12 is active during a standby mode. The standby circuit 12 provides.a stable standby voltage Voutstandby for the circuit 10, and generates substantially no current in standby mode. The bias circuit 14 is active during a bias mode and provides a stable bias voltage Voutbias for the circuit 10. The boost circuit 16 is active during the transition from standby mode to bias mode, and is effective to quickly lower or “pull down” the output voltage from Voutstandby to Voutbias.
Claims20
A high speed bias voltage generating circuit comprising:
- a first node for receiving an input signal;
- a second node for providing an output voltage;
- a first circuit that is coupled to said first node and said second node, said first circuit being adapted to provide a standby voltage and substantially no output current to said second node when said input signal has a first value;
- a second circuit that is coupled to said first node and said second node, said second circuit being adapted to provide a bias voltage to said second node when said input signal has a second value different from said first value;
- and
- a third circuit that is coupled to said first node and to said second node, said third circuit being adapted to cause said output voltage to be changed from said standby voltage to a value substantially close to said bias voltage after said input signal switches from said first value to said second value.
A high speed bias voltage generating circuit comprising:
- an input terminal that receives an input signal;
- an output terminal that provides-an output signal;
- a standby circuit portion which is coupled to said input and output terminals, which is active only when said input signal has a first value, and which is adapted to provide a standby voltage at said output terminal when active;
- bias circuit portion which is coupled to said input and output terminals, which is active only when said input signal has a second value different from said first value, and which is adapted to provide a bias voltage at said output terminal when active;
- and
- a boost circuit portion which is coupled to said input and output terminals, which is active only during a predetermined period of time after said input signal switches from said first value to said second value, and which is adapted to cause said output voltage to rapidly approach said bias voltage during said predetermined period of time.
A method for providing a bias voltage in response to an input signal, comprising the steps of:
- providing a standby voltage at an output node by use of a first circuit when said input signal has a first value;
- providing a bias voltage at said output node by use of a second circuit when said input signal has a second value;
- and
- quickly lowering the voltage at said output node from said standby voltage to said bias voltage by use of a third circuit, when said input signal switches from said first value to said second value.
Dependencies are inferred from the claim text.