US 6,548,903 B2Granted

Semiconductor integrated circuit

AssigneeFujitsu Limited

InventorsToshikazu Nakamura, Toshiya Miyo

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Abstract

In the first and second regions data not concurrently transferred is transferred by using data lines having the respective different wiring layers. The vertical positions of the data lines are reversed between the first and second regions. In the switching regions the data lines are exchanged between the first and second regions. The parasitic capacitances associated with the two data lines are practically equal to each other so that the delay times of signals transferred along the data lines are equal to each other. This can prevent a circuit malfunction due to a parasitic capacitance difference. In the semiconductor integrated circuit where memory cell arrays and sense amplifier arrays are alternately wired, forming the first and second regions over the memory cell arrays and the switching regions over the sense amplifier arrays makes it easier to exchange the vertical positions of the data lines in the switching regions.

Claims6

Dependent claims

A semiconductor integrated circuit having first and second data lines for transferring data at respective different timings, said semiconductor integrated circuit comprising:

first region(s) in which said first data line is formed in a first wiring layer above a semiconductor substrate and said second data line extending over said first data line is formed in a second wiring layer above said first wiring layer;
second region(s) in which said second data line is formed in said first wiring layer and said first data line extending over said second data line is formed in said second wiring layer;
and
switching region(s) formed between said first and second regions for connecting the first data line in said first region with the first data line in said second region, and for connecting the second data line in said first region with the second data line in said second region, wherein
in said switching region at least either of said first data lines and said second data lines are connected with each other via a third wiring layer formed above said semiconductor substrate.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/066,630Filed 6 Feb 2002
Priority: JP 2001-23090631 Jul 2001
Published: US 2003/0025122 A16 Feb 2003
Granted: 15 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/495
Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes: capacitive…
H10B 12/48
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: data lines or contacts therefor
H10B 12/482
Data lines or contacts therefor: bit lines
H10D 89/10
Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00: integrated device layouts