Semiconductor integrated circuit device, circuit design apparatus, and circuit design method
AssigneeFujitsu Limited
InventorsKenji Suzuki, Shogo Tajima
Life of this patent
Estimating the term…
Abstract
A semiconductor integrated circuit device in which wirings in different layers are connected electrically by vias and in which wiring width at a connection terminal is limited to the maximum width. A plurality of vias are arranged annularly in an area where a wiring in a lower layer and a wiring in an upper layer overlap. A pillar is generated in an area surrounded by the plurality of vias. Locating the pillar will narrow wiring width at a connection terminal for making interlayer connection. Furthermore, the plurality of vias arranged around the pillar will ensure a good connection.
Claims16
A semiconductor integrated circuit device with a multi-layer wiring structure, comprising:
- a first wiring located in a first layer;
- a second wiring located in a second layer laid over the first layer;
- a plurality of vias formed between the first layer and the second layer and arranged annularly in an area where the first wiring and the second wiring overlap;
- and
- a pillar of an insulating material which is formed in an area in the first wiring surrounded by the plurality of vias.
A circuit design apparatus for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure, the apparatus comprising:
- first virtual wiring generating means for generating a first virtual wiring being narrower than a first wiring in a first layer;
- first via generating means for generating at least one via in an area between a second wiring in a second layer laid over the first layer and the first virtual wiring generated by the first virtual wiring generating means;
- second virtual wiring generating means for generating a second virtual wiring being narrower than the second wiring in the second layer;
- and
- second via generating means for generating at least one via in an area between the first wiring and the second virtual wiring generated by the second virtual wiring generating means.
A circuit design apparatus for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure, the apparatus comprising:
- edge judging means for judging an edge of an area where a first wiring in a first layer and a second wiring in a second layer overlap;
- and
- via generating means for generating a plurality of vias in an annular area of a predetermined width from the edge.
A circuit design method for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure, the method comprising the steps of:
- generating a first virtual wiring being narrower than a first wiring in a first layer;
- generating a via in an area between a second wiring in a second layer laid over the first layer and the first virtual wiring;
- generating a second virtual wiring being narrower than the second wiring in the second layer;
- and
- generating a via in an area between the first wiring and the second virtual wiring.
A circuit design method for designing interlayer interconnection in semiconductor integrated circuits with a multi-layer wiring structure, the method comprising the steps of:
- judging an edge of an area where a first wiring in a first layer and a second wiring in a second layer overlap;
- and
- generating a plurality of vias in an annular area of a predetermined width from the edge.
Dependencies are inferred from the claim text.