Method of reducing shear stresses on IC chips and structure formed thereby

A circuit structure comprising:

• a substrate having a recess in a surface thereof;
• an integrated circuit chip disposed in the recess, the chip having a peripheral surface region adjacent outer edges thereof, an active region surrounded by the peripheral surface region, and contact pads on the peripheral surface region;
• a moat defined by a residual portion of the recess surrounding the edges of the chip;
• a dielectric polymer layer overlying at least a portion of the substrate and the peripheral surface region of the chip but being absent from the active region of the chip, the polymer layer bridging the moat surrounding the edges of the chip;
• conductive vias in the polymer layer;
• and
• metal interconnect lines on a surface of the polymer layer and electrically interconnected with the contact pads through the vias;
• wherein the surface of the polymer layer comprises trenches that surround the peripheral surface region of the chip, each of the trenches being continuous around the chip and uniformly spaced from the outer edges of the chip, the interconnect lines lying on the surface of the polymer layer and the trenches so as to have serpentine portions within the trenches, at least one of the trenches residing in a portion of the polymer layer bridging the moat.