US 6,548,885 B2 · Semiconductor integrated circuit device and process for manufacturing the same · patentgrep

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Abstract

A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Claims43

Dependent claims

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET, each having a gate electrode formed over a semiconductor substrate and a source region and a drain region formed in said substrate;
a first second-channel MISFET and a second second-channel MISFET, each having a gate electrode formed over said semiconductor substrate and each having a source region and a drain region formed in said substrate;
a first insulating film formed on the gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to said drain region of said first first-channel MISFET, said drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to said drain region of said second first-channel MISFET, said drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
and
a wiring line formed on said dielectric film and being electrically connected to said source region of said first first-channel MISFET and said source region of said second first-channel MISFET,
wherein said first conductive film, said dielectric film, and said wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said wiring line comprise another capacitor element, and
wherein said wiring line is formed to cover substantially all of the first and second conductive films.

8 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell of a static random access memory, each having a gate electrode;
a first second-channel MISFET and a second second channel MISFET of said memory cell, each having a gate electrode comprised of a same level layer as said gate electrodes of said first-channel MISFETs;
a first insulating film formed on the gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
and
a wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET,
wherein said first conductive film, said dielectric film, and said wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said wiring line comprise another capacitor element, and
wherein said wiring line is formed over said first and said second conductive films to substantially completely cover said first and said second conductive films.

8 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET, each having a gate electrode comprised of a same level layer as said gate electrodes of said first-channel MISFETs;
a first insulating film formed on the gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
and
a wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET,
wherein said first conductive film, said dielectric film, and said wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said wiring line comprise another capacitor element, and
wherein said wiring line is formed to cover said first and said second conductive films, said drain region of said first first-channel MISFET, and said drain region of said second first-channel MISFET.

8 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET, each having a gate electrode formed over a semiconductor substrate and each having a source region and a drain region formed in the substrate;
a first second-channel MISFET and a second second-channel MISFET, each having a gate electrode formed over said substrate and each having a source region and a drain region formed in said substrate;
a first insulating film formed on the gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to said drain region of said first first-channel MISFET, said drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to said drain region of said second first-channel MISFET, said drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
and
a wiring line formed on said dielectric film and being electrically connected to said source region of said first first-channel MISFET and said source region of said second first-channel MISFET,
wherein said first conductive film, said dielectric film, and said wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said wiring line comprise another capacitor element, and
wherein said wiring line extends over said first conductive film and said second conductive film, said drain region of said first first-channel MISFET, said drain region of said second first-channel MISFET, said drain region of said first second-channel MISFET, and said drain region of said second second-channel MISFET.

8 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line and a third wiring line each formed on said second insulating film and each extending over said memory cell,
said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET, and
said third wiring line being electrically connected to said first wiring line,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said second conductive film, said dielectric film, and said first wiring line comprise another capacitor element.

11 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line and a third wiring line each formed on said second insulating film and each extending over said memory cell,
said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET, and
said third wiring line being electrically connected to said first wiring line,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said first wiring line is formed over said first conductive film and said second conductive film to cover substantially all of said first conductive film and said second conductive film.

12 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line and a third wiring line each formed on said second insulating film and each extending over said memory cell,
said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET, and
said third wiring line being electrically connected to said first wiring line,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said first wiring line extends over said first conductive film and said second conductive film, said drain region of said first first-channel MISFET, said drain region of said second first-channel MISFET, said drain region of said first second-channel MISFET, and said drain region of said second second-channel MISFET.

12 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETS;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line formed on said second insulating film and extending over said memory cell,
said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said second conductive film, said dielectric film, and said first wiring line comprise another capacitor element.

10 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETS;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed on said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line formed on said second insulating film and extending over said memory cell,
said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said first wiring line is formed over said first conductive film and said second conductive film to cover substantially all of said first conductive film and said second conductive film.

11 more elements

A semiconductor integrated circuit device comprising:

a first first-channel MISFET and a second first-channel MISFET of a memory cell, each having a gate electrode;
a first second-channel MISFET and a second second-channel MISFET of said memory cell, each having a gate electrode;
a first insulating film formed on said gate electrodes of said first and second first-channel MISFETs and said first and second second-channel MISFETs;
a first conductive film formed on said first insulating film and being electrically connected to a drain region of said first first-channel MISFET, a drain region of said first second-channel MISFET, said gate electrode of said second first-channel MISFET, and said gate electrode of said second second-channel MISFET;
a second conductive film formed oh said first insulating film and being electrically connected to a drain region of said second first-channel MISFET, a drain region of said second second-channel MISFET, said gate electrode of said first first-channel MISFET, and said gate electrode of said first second-channel MISFET;
a dielectric film formed on said first conductive film and said second conductive film;
a first wiring line formed on said dielectric film and being electrically connected to a source region of said first first-channel MISFET and a source region of said second first-channel MISFET;
a second insulating film formed on said first wiring line;
and
a second wiring line formed on said second insulating film and extending over said memory cell, said second wiring line being electrically connected to a source region of said first second-channel MISFET and a source region of said second second-channel MISFET,
wherein said first conductive film, said dielectric film, and said first wiring line comprise a capacitor element,
wherein said second conductive film, said dielectric film, and said first wiring line comprise a capacitor element, and
wherein said first wiring line extends over said first conductive film and said second conductive film, said drain region of said first first-channel MISFET, said drain region of said second first-channel MISFET, said drain region of said first second-channel MISFET, and said drain region of said second second-channel MISFET.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/755,184Filed 8 Jan 2001 · continuation
Priority: JP 6-11492527 May 1994
Published: US 2001/0019641 A16 Sep 2001
Granted: 15 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

Family

Application08/451,117Parent of this division · filed 25 May 1995
Application08/880,736Parent of this continuation · filed 23 Jun 1997
Application09/334,266Parent of this continuation · filed 16 Jun 1999
US 2001/0019641 A1Pre-grant publication · published 6 Sep 2001
US 6,211,004 B1Parent of this continuation
US 5,946,565 AParent of this continuation
Application08/880,736Parent of this division
US 5,754,467 AParent of this division
US 6,548,885 B2This patent

From the US filing history. Foreign family members aren’t listed.

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