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US 6,548,883 B2Granted
Reduced RC between adjacent substrate wiring lines
AssigneeMicron Technology, Inc.
InventorJohn H. Givens
Life of this patent
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AssigneeMicron Technology, Inc.
InventorJohn H. Givens
Estimating the term…
A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are “T-topped” (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.
A semiconductor substrate having a spacing between at least two adjacent wiring lines, the substrate comprising:
A semiconductor substrate comprising:
Dependencies are inferred from the claim text.