US 6,548,875 B2Granted

Sub-tenth micron misfet with source and drain layers formed over source and drains, sloping away from the gate

AssigneeKabushiki Kaisha Toshiba

InventorAkira Nishiyama

Life of this patent

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Abstract

A semiconductor device having a low channel resistance without degrading transistor characteristics even for the 0.1 μm generation or later, and also: a manufacturing method of the device. The method includes fabricating source/drain electrodes and a gate electrode without using selective metal growth methods. Further, after forming the gate electrode, a semiconductor film is temporarily formed selectively in source/drain regions. A dielectric film is next deposited on the substrate and then, the surface is etched by chemical/mechanical polish (CMP) techniques to the extent that the semiconductor film is exposed on the surface. The semiconductor film is then partly etched until its midway portion along the thickness is removed. Thereafter, a desired metal or silicide is deposited on the entire surface. Next, CMP etching is performed to form electrodes, while letting the electrodes reside on or over the source/drain semiconductor layers and a gate insulation layer.

Claims8

Dependent claims

A transistor comprising:

a semiconductor substrate;
a gate insulation film formed on the semiconductor substrate;
a gate electrode formed on the gate insulation film;
a channel region formed in the semiconductor substrate below the gate insulation film;
a source region and a drain region formed to be spaced apart from each other in the semiconductor substrate, said channel region being between the source region and the drain region;
a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the semiconductor substrate;
a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and the surface of the semiconductor substrate;
a source electrode buried in the concave portion at the upper portion of the source semiconductor layer;
and
a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer,
wherein said gate electrode, said drain electrode and said source electrode are formed of the same material selected from the group consisting of metal and metal silicide.

8 more elements

A semiconductor device comprising:

a common semiconductor substrate;
an n-channel MISFET on the common semiconductor substrate and including:
a gate insulation film formed on the common semiconductor substrate,
a gate electrode formed on the gate insulation film,
a channel region formed in the common semiconductor substrate below the gate insulation film,
a source region and a drain region formed to be spaced apart from each other in the common semiconductor substrate, said channel region being between the source region and the drain region,
a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,
a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upped portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,
a source electrode buried in the concave portion at the upper portion of the source semiconductor layer, and
a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer;
and
a p-channel MISFET on the common semiconductor substrate including:
a gate insulation film formed on the common semiconductor substrate,
a gate electrode formed on the gate insulation film,
a channel region formed in the common semiconductor substrate below the gate insulation film,
a source region and a drain region formed to be spaced apart from each other in the common semiconductor substrate, said channel region being between the source region and the drain region,
a source semiconductor layer formed over the source region, said source semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the source semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,
a drain semiconductor layer formed over the drain region, said drain semiconductor layer having a concave portion at an upper portion thereof and including an acute angle defined between a side face of the drain semiconductor layer facing the gate electrode and a surface of the common semiconductor substrate,
a source electrode buried in the concave portion at the upper portion of the source semiconductor layer, and
a drain electrode buried in the concave portion at the upper portion of the drain semiconductor layer,
wherein said gate electrode, said drain electrode and said source electrode of said n-channel MISFET are made of same material selected from metal and metal silicide, and
wherein said gate electrode, said drain electrode and said source electrode of said p-channel MISFET are made of same material selected from the group consisting of metal and metal silicide and said source electrode, said drain electrode and said gate electrode of said n-channel MISFET are different material from said source electrode, said drain electrode and said gate electrode of said p-channel MISFET.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/798,924Filed 6 Mar 2001
Priority: JP 2000-0601846 Mar 2000
Published: US 2002/0008261 A124 Jan 2002
Granted: 15 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 30/608
Having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs: having non-planar bodies, e.g. having recessed gate electrodes
H10D 62/405
Crystalline structures: orientations of crystalline planes