Higher voltage transistors for sub micron CMOS processes
AssigneeTexas Instruments Incorporated
InventorsAlec Morton, Taylor Efland, Chin-yu Tsai, Jozef C. Mitros, Dan M. Mosher, Sam Shichijo, Keith Kunz
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Abstract
An intergrated circuit drain extension transistor for sub micron CMOS processes. A transistor gate (40) is formed over a CMOS n-well region (80) and a CMOS p-well region (70) in a silicon substrate (10). Transistor source regions (50), (140) and drain regions (55), (145) are formed in the various CMOS well regions to form drain extension transistors where the CMOS well regions (70), (80) serve as the drain extension regions of the transistor.
Claims32
An integrated circuit drain extended transistor comprising:
- a semiconductor substrate comprising a first well region of a first conductivity type adjacent to a second well region of a second conductivity type;
- a transistor gate partially overlapping said first well region and said second well region;
- a transistor source region of a second conductivity type adjacent to said transistor gate and contained in said first well region;
- and
- a transistor drain region of a second conductivity type contained in said second well region.
An integrated circuit drain extended transistor comprising:
- a semiconductor substrate comprising a first p-type compensated well region contained in a core CMOS n-well region wherein said first p-type compensated well region comprises a core CMOS n-well implant and a core CMOS p-well implant;
- a transistor gate partially overlying said first p-type compensated well region and said core CMOS n-well region;
- a p-type transistor source region adjacent to said transistor gate and contained in said core CMOS n-well region;
- and
- a p-type transistor drain region contained in said p-type compensated well region.
An integrated circuit drain extended transistor comprising:
- a semiconductor substrate comprising a first well region of a first conductivity type adjacent to a second well region of a second conductivity type wherein said first well region is separated from said second well region by a spacing distance;
- a transistor gate partially overlapping said first well region and said second well region;
- a transistor source region of a second conductivity type adjacent to said transistor gate and contained in said first well region;
- and
- a transistor drain region of a second conductivity type contained in said second well region.
An integrated circuit drain extended transistor comprising:
- a semiconductor substrate containing a first well region;
- a transistor gate partially overlapping said first well region;
- a silicide block structure partially overlapping said transistor gate and said first well region;
- and
- a transistor drain region contained in said first well region and positioned adjacent to said silicide block structure.
A drain extended transistor comprising:
- a semiconductor substrate comprising a first well region of a first conductivity type adjacent to a second well region of a second conductivity type;
- a transistor gate partially overlapping said first well region and said second well region;
- a transistor source region of a second conductivity type adjacent to said transistor gate and contained in said first well region;
- a lightly doped region of a second conductivity type contained in said first well region, adjacent to said transistor source region, and underlying a portion of said transistor gate;
- and
- a transistor drain region of a second conductivity type contained in said second well region.
An integrated circuit drain extended transistor comprising:
- a semiconductor substrate comprising a first n-type compensated well region contained in a core CMOS p-well region wherein said first n-type compensated well region comprises a core CMOS p-well implant and a core CMOS n-well implant;
- a transistor gate partially overlying said first n-type compensated well region and said core CMOS p-well region;
- a p-type transistor source region adjacent to said transistor gate and contained in said core CMOS p-well region;
- and
- a n-type transistor drain region contained in said n-type compensated well region.
Dependencies are inferred from the claim text.