US 6,548,871 B1Granted

Semiconductor device achieving reduced wiring length and reduced wiring delay by forming first layer wiring and gate upper electrode in same wire layer

AssigneeMitsubishi Denki Kabushiki Kaisha

InventorsKatsuyuki Horita, Takashi Kuroi, Yasuyoshi Itoh, Katsuomi Shiozawa

Life of this patent

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Abstract

Two source/drain regions (20) belonging to separate elements which are adjacent to each other are connected through a metal layer (14) having the same height as a height of a metal layer (10) forming a part of a gate electrode. In a manufacturing process, an insulating layer (8) is made of other material than and inserted between two insulating layers (7) and (16). The two insulating layers (7) and (16)function as molds for burying the metal layers (10), (14) and (15) therein and made of the same material. The metal layer (14) can therefore be formed at the same height as the height of the metal layer (10). Accordingly, portions to be connected through a wiring which are provided at a comparatively short distance are connected while reducing a wiring capacity.

A semiconductor device comprising:

a) a semiconductor substrate having a main surface;
and
b) a plurality of element regions set along said main surface of said semiconductor substrate, each of said element regions including:
a channel region selectively provided in said main surface;
a pair of source/drain regions selectively provided in said main surface with said channel region interposed therebetween;
a gate insulating film provided on said channel region;
a conductive layer provided on said gate insulating film;
a first insulating layer which has a first opening selectively penetrating from an upper surface of said first insulating layer to a lower surface of said first insulating layer over a surface of said pair of source/drain regions, said first insulating layer accommodating said conductive layer;
a second insulating layer provided on said first insulating layer and formed of a material different from a material of said first insulating layer, the second insulating layer selectively defining a second opening penetrating from an upper surface of said second insulating layer to a lower surface of said second insulating layer so as to communicate with said first opening and a surface of said conductive layer;
a third insulating layer provided on said second insulating layer and formed of a material different from said material of said second insulating layer, said third insulating layer selectively defining a third opening which is opened to include said second opening in said second insulating layer, said third opening penetrating from an upper surface of said third insulating layer to a lower surface of said third insulating layer so as to communicate with said first and second openings;
and
a metal layer, buried in said first, second and third openings, the metal layer including:
(1) a gate upper electrode provided on said conductive layer;
and
(2) a wiring layer electrically connected to wiring layers in other of said element regions;
wherein an upper surface of said first insulating layer is arranged on a level with that of said conductive layer.

13 more elements

Facts

Application

09/543,349Filed 5 Apr 2000

Priority

JP 11-30510827 Oct 1999

Published

US 2003/0075744 A124 Apr 2003

Granted

15 Apr 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10D 84/0149
The components including insulated gates, e.g. IGFETs: manufacturing their interconnections or electrodes, e.g. source or drain electrodes
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10W 20/081
Of dielectric parts thereof: by forming openings in the dielectric parts

Abstract

Claims8