Semiconductor device
AssigneeHynix Semiconductor Inc.
InventorHi Deok Lee
Life of this patent
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Abstract
In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity region and the second impurity region. At least two gate electrodes are formed on the gate insulating layer, and are insulated from one another by an intergate insulation layer.
Claims12
A semiconductor device, comprising:
- a first impurity region and a second impurity region formed in a surface of a semiconductor substrate at a regular interval;
- a gate insulating layer formed on the semiconductor substrate between the first impurity region and the second impurity region said gate insulating layer having a uniform thickness;
- and
- a plurality of adjacent gate electrodes formed on said gate insulating layer, said plurality of gate electrodes having identical size and shape.
A semiconductor device having two NMOS transistors serially connected to each other, the semiconductor device comprising:
- a first n-type impurity region and a second n-type impurity region formed in a surface of a semiconductor substrate at a regular interval;
- a gate insulating layer formed on the semiconductor substrate between the first n-type impurity region and the second n-type impurity region said gate insulating layer having a uniform thickness;
- and
- a plurality of adjacent gate electrodes formed on said gate insulating layer, said plurality of gate electrodes having identical size and shape.
A semiconductor device having two PMOS transistors serially connected to each other, the semiconductor device comprising:
- a first p-type impurity region and a second p-type impurity region formed in a surface of a semiconductor substrate at a regular interval;
- a gate insulating layer formed on the substrate between the first p-type impurity region and the second p-type impurity region said gate insulating layer having a uniform thickness;
- and
- a plurality of adjacent gate electrodes formed on said gate insulating layer, said plurality of gate electrodes having identical size and shape.
Dependencies are inferred from the claim text.