High density MOS technology power device

#1. Field of the Invention

#The present invention relates to either discrete devices or integrated power semiconductor devices including MOS-gated power devices such as, for example, power MOSFETS, IGBTs, MOS-gated thyristors or other MOS-gated power devices. In particular, the invention relates to a MOS-gated power device having a smaller minimum dimension Lp that yields an increased density of MOS-gated power devices per unit area.

#2. Discussion of the Related Art

#The foregoing and other objects and advantages will be more fully appreciated from the following drawing in which:

#FIG. 1 is a cross-sectional view of a MOS technology power device according to the prior art;

#FIG. 2 is a top-plan view of a portion of MOS technology power device according to a first embodiment of the present invention;

#As discussed above, FIG. 1 is a cross-sectional view of a MOS technology power device chip according to the related art. The power device chip includes a heavily doped semiconductor substrate 1, and a lightly doped epitaxial layer 2 of a first conductivity type formed over the semiconductor substrate. The MOS technology power device includes a plurality of elementary functional units formed in the epitaxial layer 2. Two of the elementary functional units are illustrated in FIG. 1.

#Each elementary functional units includes a body region 3 of a second conductivity type formed in the epitaxial layer 2. Each body region 3 can have a polygonal layout, such as for example a square or a hexagonal shape, or can be formed as an elongated stripe that has a longitudinal direction in a direction into the Figure. In other words, FIG. 1 is a cross-sectional view in a direction transverse to a length of the elongated stripes. The body region includes a central heavily doped portion 4, called a “deep body region”, and a lateral portion 5, having a lower dopant concentration, and which forms a channel region of the elementary functional unit. A doping level of the lateral portion 5 of the body region determines a threshold voltage of the power device. The threshold voltage is the voltage at which the device begins to conduct. Inside each body region 3, is a source region 6 of the same conductivity type as the epitaxial layer 2. A thin oxide layer 7 (a gate oxide layer) and a polysilicon layer 8 cover a surface of portions of the epitaxial layer 2 between the body regions 3 of the two elementary functional units, and extend over the lateral portions 5 of the body regions 3 in each functional unit. A window 12 is provided in the polysilicon and gate oxide layers 8, 7 over the body region 3, and in particular over a surface of each source region and a surface of the deep body region. The polysilicon layer 8 is covered by a dielectric layer 9 in which a contact window 11 is opened over each body region 3, to expose a surface of an inner-portion of each of the source regions and a surface of the deep body region. A metal layer 10 making up the source electrode of the power device is placed over the dielectric layer and contacts the surface of the source regions 6 and the surface of the deep body region 4 through the contact window.

#A size of each elementary functional unit of the MOS power device is a function of a dimension Lp of the window 12 in the polysilicon layer 8 and the gate oxide layer 7. As discussed above and illustrated in FIG. 1, the dimension Lp is a function of the features “a” and “t” as defined in equation (1):