Lateral DMOS transistor integratable in semiconductor power devices
AssigneeSTMicroelectronics S.r.l.
InventorDavide Patti
Life of this patent
Estimating the term…
Abstract
The lateral DMOS transistor is integratable in a semiconductor power device comprising a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current ID flowing between the source region and the drain region of the lateral DMOS transistor.
Claims20
A power device comprising:
- a first semiconductor region having a first type of conductivity;
- a second semiconductor region having a second type of conductivity and being set on top of said first semiconductor region;
- and
- a lateral DMOS transistor formed in said second semiconductor region, said lateral DMOS transistor comprising:
- first and second conduction regions formed in said second semiconductor region;
- a body region surrounding one of said first and second conduction regions;
- an insulating region formed in said second semiconductor region between said first and second conduction regions, extending in depth from a top surface of said second semiconductor region as far as said first semiconductor region, said insulating region presenting at least one interruption defining a channeling region for charge carriers flowing between said first and second conduction regions.
A device comprising:
- a semiconductor substrate having a first type of conductivity;
- a layer of semiconductor material on the substrate, having a second type of conductivity;
- a body region having the first type of conductivity, formed in the layer;
- a first conduction region having the second type of conductivity, formed in the body region;
- a second conduction region having the second type of conductivity, formed in the layer;
- an insulating region formed in the layer between the body region and the second conduction region, the insulating region having an interruption;
- and
- a channeling region positioned in the interruption and structured to allow conduction when the device is activated.
A device comprising:
- a semiconductor substrate having a first type of conductivity;
- a layer of semiconductor material on the substrate, having a second type of conductivity;
- first and second body regions having the first type of conductivity, formed in the layer;
- first and second source conduction region having the second type of conductivity, formed in the first and second body regions, respectively;
- a common drain conduction region having the second type of conductivity, formed in the layer between and removed from the body regions;
- and
- first and second insulating regions, formed in the layer between the first body region and the common drain conduction region and the second body region and the common drain conduction region, respectively, and extending from an upper surface of the layer to the substrate, the first and second insulating regions each having an interruption defining a channeling region.
Dependencies are inferred from the claim text.