Integrated circuitry and methods of forming circuitry

A circuit construction comprising:

• a substrate having a memory array region and a peripheral region that is peripheral to the memory array region;
• a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer;
• the capacitor dielectric layer being between the storage node and the cell plate layer;
• and
• an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and the substrate in the peripheral region, the electrical interconnect extending between the cell plate layer and the substrate.

An integrated circuit comprising:

• a capacitor and a conductive plug, the conductive plug and capacitor comprising:
• a first common and continuous layer;
• a second common and continuous layer over the first common and continuous layer;
• and
• a third common and continuous layer over the second common and continuous layer;
• and
• wherein the first common and continuous layer comprises Ti, the second common and continuous layer comprises a metal nitride, and the third common and continuous layer comprises one or more of W, Al and Cu;
• the first, second and third common and continuous layers being chemically different from one another.

An integrated circuit comprising:

• a capacitor and a conductive plug, the conductive plug and capacitor comprising:
• a first common and continuous layer;
• a second common and continuous layer over the first common and continuous layer;
• and
• a third common and continuous layer over the second common and continuous layer;
• and
• a substrate;
• an insulative layer over the substrate;
• the conductive plug extending through the insulative layer;
• the capacitor comprising a storage node extending through the insulative layer and a cell electrode over the insulative layer;
• and
• the cell electrode comprising the first common and continuous layer.

A circuit construction comprising:

• a substrate having a memory array region and a peripheral region that is peripheral to the memory array region;
• a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer;
• the capacitor dielectric layer being between the storage node and the cell plate layer;
• an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and extending between the cell plate layer and the substrate;
• and
• wherein the electrical interconnect extends from the cell plate layer to the substrate.

A circuit construction comprising:

• a substrate having a memory array region and a peripheral region that is peripheral to the memory array region;
• a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer;
• the capacitor dielectric layer being between the storage node and the cell plate layer;
• an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and extending between the cell plate layer and the substrate;
• and
• a transistor proximate the peripheral region of the substrate, the transistor comprising a source/drain region, the electrical interconnect extending from the cell plate layer to the source/drain region.

A circuit construction comprising:

• a substrate having a memory array region and a peripheral region that is peripheral to the memory array region;
• a capacitor construction over the memory array region of the substrate, the capacitor construction comprising a storage node, a capacitor dielectric layer and a cell plate layer;
• the capacitor dielectric layer being between the storage node and the cell plate layer;
• an electrical interconnect over the peripheral region, the interconnect being electrically connected to the cell plate layer and extending between the cell plate layer and the substrate;
• and
• wherein the electrical interconnect and cell plate layer comprise at least two common and continuous layers.