Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsFumio Horiguchi, Takashi Ohsawa, Yoshihisa Iwata, Takashi Yamada
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Abstract
Each of MIS transistors of a semiconductor memory device has a semiconductor layer (12); a source region (15) formed in the semiconductor layer; a drain region (14) formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state; a first gate (13) which forms a channel in the channel body; a second gate (20) formed so as to control a potential of the channel body by a capacitive coupling; and a high concentration region (21) formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body.
Claims26
A semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
- a semiconductor layer;
- a source region formed in the semiconductor layer;
- a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
- a first gate which forms a channel in the channel body;
- a second gate formed so as to control a potential of the channel body by a capacitive coupling;
- and
- a high concentration region formed in the channel body on the second gate side, impurity concentration of the high concentration region being higher than that of the channel body,
- wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential.
A semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
- a semiconductor layer;
- a source region formed in the semiconductor layer;
- a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
- and
- a first gate which forms a channel in the channel body,
- wherein characteristics of the MIS transistor in the case where a channel current flows from the source region to the drain region is different from characteristics of the MIS transistor in the case where a channel current flows from the drain region to the source region, even when the same potential is applied to the first gate, and
- wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential, the first data state being set by the impact ionization generated near a drain junction or by a drain leakage current caused by the first gate, the second data state being set by sending a forward bias current between the drain region and the channel body.
A semiconductor memory device including MIS transistors to constitute memory cells, each of the MIS transistors comprising:
- a semiconductor layer;
- a source region formed in the semiconductor layer;
- a drain region formed apart from the source region in the semiconductor layer, the semiconductor layer between the source region and the drain region serving as a channel body in a floating state;
- and
- a gate which forms a channel in the channel body,
- wherein the MIS transistor has a first data state in which the channel body has a first potential and a second data state in which the channel body has a second potential, the first data state being set by a drain leakage current caused by the gate to which a negative potential is applied, the second data state being set by sending a forward bias current between the drain region and the channel body.
Dependencies are inferred from the claim text.