US 6,548,847 B2 · SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A FIRST WIRING STRIP EXPOSED THROUGH A CONNECTING HOLE, A TRANSITION-METAL FILM IN THE CONNECTING HOLE AND AN ALUMINUM WIRING STRIP THEREOVER, AND A TRANSITION-METAL NITRIDE FILM BETWEEN THE ALUMINUM WIRING STRIP AND THE TRANSITION-METAL FILM

Semiconductor integrated circuit device having a first wiring strip exposed through a connecting hole, a transition-metal film in the connecting hole and an aluminum wiring strip thereover, and a transition-metal nitride film between the aluminum wiring strip and the transition-metal film

AssigneesHitachi, Ltd., Hitachi VLSI Engineering Corp.

InventorsJun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane

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Abstract

Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.

Claims33

Dependent claims

A semiconductor integrated circuit device comprising:

a semiconductor substrate having a main surface;
an MISFET having a gate electrode over said main surface of said semiconductor substrate, and a source region and a drain region formed in said semiconductor substrate at both sides of said gate electrode;
a first insulating film formed over said MISFET;
a first wiring strip formed over said first insulating film;
a second insulating film formed over said first wiring strip and having a connecting hole exposing said first wiring strip;
a tungsten film selectively formed in said connecting hole;
an aluminum wiring strip formed overlying said tungsten film and said second insulating film;
and
a titanium nitride film formed directly on said tungsten film, said aluminum wiring strip being formed directly on said titanium nitride film.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/899,921Filed 9 Jul 2001 · division

Priority

JP 1-6584920 Mar 1989

Published

US 2002/0017669 A114 Feb 2002

Granted

15 Apr 2003

Term ends

Not estimatedThe source records don’t support an estimate.

Classification43 codes

H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
G03F 7/70333
Resolution enhancement techniques not otherwise provided for, e.g. darkfield imaging, interfering beams, spatial frequency multiplication,…: focus…
G03F 9/70
Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically: for…
H10D 1/68
Capacitors: capacitors having no potential barriers

Family

Application07/496,330Parent of this division · filed 20 Mar 1990

Application07/954,142Parent of this division · filed 30 Sep 1992

Application08/230,021Parent of this division · filed 19 Apr 1994

Application08/458,481Parent of this continuation · filed 2 Jun 1995

Application08/460,931Parent of this continuation · filed 5 Jun 1995

Application08/943,729Parent of this continuation · filed 3 Oct 1997

Application09/459,921Parent of this division · filed 14 Dec 1999

US 2002/0017669 A1Pre-grant publication · published 14 Feb 2002

Application09/459,921Parent of this continuation

Application08/460,931Parent of this division

Application08/458,481Parent of this division