US 6,548,839 B1 · LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability

Abstract

An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.

Claims9

Dependent claims

An LDMOS transistor array structure comprising:

an array that includes a plurality of alternating source regions and a plurality of alternating drain regions formed in a semiconductor substrate to define a checkerboard pattern of said alternating source and drain regions;
a conductive source interconnect structure formed in electrical contact with each of the plurality of source regions in the array to electrically connect said source regions in parallel;
a conductive drain interconnect structure formed in electrical contact with each of the plurality of drain regions in the array to electrically connect said drain regions in parallel;
and
a drain ring structure formed in the semiconductor substrate around and spaced apart from the periphery of the checkerboard pattern.

2 more elements

Dependencies are inferred from the claim text.

LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability

Life of this patent

LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability

Life of this patent

Abstract

Claims9