Method of forming contact plugs
AssigneeProMOS Technologies Inc.
InventorsHsin-Tang Peng, Yung-Ching Wang
Life of this patent
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Abstract
A method of forming contact plugs is used on a semiconductor substrate with at least four adjacent gate conducting structures, wherein a second gate conducting structure and a third gate conducting structure are formed within an active area. First, the gap between the second gate conducting structure and the third gate conducting structure is filled with a first conductive layer. Then, an inter-layered dielectric (ILD) layer with a planarized surface is formed on the entire surface of the substrate to cover the first conductive layer. Next, a bitline contact hole is formed in the ILD layer to expose the first conductive layer. Thereafter, the bitline contact hole is filled with a second conductive layer to serve as a bitline contact plug.
Claims11
A method of forming contact plugs, comprising steps of:
- (a) providing a semiconductor substrate having a first gate conducting structure, a second gate conducting structure, a third gate conducting structure and a fourth gate conducting structure arranging in sequence, wherein the second gate conducting structure and the third gate conducting structure are formed within an active area;
- (b) filling the gap between the second gate conducting structure and the third gate conducting structure with a first conductive layer;
- (c) forming an inter-layered dielectric (ILD) layer with a planarized surface on the entire surface of the substrate to cover the first conductive layer and fill the gap between the first gate conducting structure and the second gate conducting structure and the gap between the third gate conducting structure and the fourth gate conducting structure;
- (d) forming a bitline contact hole in the ILD layer to expose the first conductive layer;
- (e) filling the bitline contact hole with a second conductive layer to serve as a bitline contact plug.
Dependencies are inferred from the claim text.