Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
AssigneeTexas Instruments Incorporated
InventorsHiroaki Niimi, Douglas T. Grider, Rajesh Khamankar
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AssigneeTexas Instruments Incorporated
InventorsHiroaki Niimi, Douglas T. Grider, Rajesh Khamankar
Estimating the term…
An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.
A method for forming an integrated circuit structure, comprising the steps of:
Dependencies are inferred from the claim text.
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Containing silicon: the material being a silicon oxide, e.g. SiO2
On single crystalline silicon, e.g. chemical oxidation using a liquid: with a treatment, e.g. annealing, after the formation of the insulator and…
On single crystalline silicon, e.g. chemical oxidation using a liquid: in a nitrogen-containing ambient, e.g. N2O oxidation
Characterised by the insulator, e.g. by the gate insulator: the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
Term ended 20 Jun 2021 (estimated)
The present invention is related in general to the field of electronic systems and semiconductor devices and more specifically to the fabrication and processing of ultra-thin gate dielectric layers.
The trend in semiconductor technology to double the functional complexity of its products every 18 months (Moore's “law”), which is still valid today after having dominated the industry for the last three decades, has several implicit consequences. First, the cost per functional unit should drop with each generation of complexity so that the cost of the product with its doubled functionality would increase only slightly. Second, the higher product complexity should largely be achieved by shrinking the feature sizes of the chip components while holding the package dimensions constant; preferably, even the packages should shrink. Third, the increased functional complexity should be paralleled by an equivalent increase in reliability of the product. And fourth, but not least, the best financial profit rewards were held out for the ones who were ahead in the marketplace in reaching the complexity goal together with offering the most flexible products for application.
The scaling of the components in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric, commonly silicon dioxide (SiO2) to be reduced. Thinning of the gate dielectric provides a smaller barrier to dopant diffusion from a poly-silicon gate structure (or metal diffusion from a metal gate structure) through the underlying dielectric, often resulting in devices with diminished electrical performance and reliability. In ultra-thin dielectric layers, interfaces with their unwelcome electronic states and carrier traps may finally dominate the electrical characteristics.
FIGS. 1, 2 and 3 are schematic cross sections of an integrated circuit structure as it is fabricated following the flow of process steps 1, 2 and 3 of the first embodiment of the invention.
FIG. 2 further indicates details of the nitridation process step.
FIG. 3 further indicates options and details of the re-oxidation and annealing process step.
The present invention is related to U.S. Pat. No. 6,136,654, issued on Oct. 24, 2000 (Kraft et al., “Method of Forming Thin Silicon Nitride or Silicon Oxynitride Gate Dielectrics”).
FIGS. 1, 2 and 3 illustrate the 3-step process flow of growing, nitriding, and annealing ultra-thin oxide layers according to the invention. The following description is centered around two embodiments of the invention, the process features and the formation of a gate dielectric, the methods of the invention are not limited to gate dielectrics. The embodiments can be used to form other layers required in the production of semiconductor devices. For example, the invention can be used to form the dielectric material in a capacitor structure, or to isolate conductive structures. Furthermore, the semiconductor does not necessarily have to be silicon (n-type or p-type), but may be silicon germanium, gallium arsenide or another III-V compound, or another compound material used in semiconductor device manufacturing.
In FIG. 1, the substrate 101 is preferably a silicon substrate or an epitaxial silicon layer formed on a silicon substrate. It may generally be a substrate with a semiconductor surface 102. An insulating layer 103 is formed on surface 102. Layer 103 contains oxygen, and is preferably silicon dioxide SiO2. Other oxygen-containing insulating materials for layer 103 include oxynitride and other insulators. Preferably, layer 103 is grown by the process step 104 of rapid thermal oxidation in a furnace. The preferred thickness range is between 0.8 and 2.0 nm. Consequently, layer 103 is classified as “ultra-thin”. While the following description of the invention also holds for deposited insulating layers 103, the electrical quality of deposited ultra-thin oxygen-containing layers has so far been inferior to thermally grown layers.