Method to reduce the gate induced drain leakage current in CMOS devices

A method for forming within a silicon semiconductor substrate, employed within an integrated circuit microelectronics fabrication, complementary metal-oxide-silicon (CMOS) field effect transistor (FET) devices comprising:

• providing a silicon semiconductor substrate of one polarity;
• forming within the silicon substrate an active device well, of opposite polarity, defined by field oxide dielectric isolation regions;
• forming over the silicon substrate active device region well silicon oxide gate oxide dielectric layers;
• forming over the silicon oxide gate oxide dielectric layers a patterned polycrystalline silicon gate electrode layer;
• thermally oxidizing the polycrystalline gate electrode layer and the silicon substrate to form a thicker silicon oxide dielectric layer at the edge and sides of the patterned polycrystalline silicon gate electrode layer and the silicon substrate regions beyond the gate electrode;
• forming spacers by etching back the silicon oxide dielectric layer beyond the edge of the patterned gate electrode layer;
• using spacers as a mask to implant ions to define shallow junction regions adjacent to the patterned gate electrode layer;
• and
• forming source and drain regions employing ion implantation using said spacers as a mask.

A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a field effect transistor (FET) device with attenuated drain leakage, short channel effect and punch-through leakage current comprising:

• providing a silicon semiconductor substrate;
• forming within the silicon semiconductor substrate field oxide isolation regions defining an active device region within said substrate;
• forming over the active region a silicon oxide gate oxide insulation layer;
• forming over the gate oxide insulation layer a patterned polycrystalline silicon layer which constitutes a gate electrode pattern;
• thermally oxidizing the silicon substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and beyond;
• forming spacers by etching back by means of anisotropic self-aligned etching the thicker silicon oxide layer at the edge of the gate electrode and beyond;
• using said spacers as a mask to implant ions to define shallow source and drain extension regions;
• and
• forming source and drain regions employing ion implantation using said spacers as a mask;
• wherein the anisotropic self-aligned etch back process employs a plasma etching environment consisting of:
• CF4 or CHF3 etching gasses;
• temperature from between about 10 to about 200 degrees centigrade;
• power from between about 100 to about 1000 watts;
• and
• pressure from between about 1 to about 5000 milliTorr.

A method for forming within a silicon semiconductor substrate, employed within an integrated circuit microelectronics fabrication, complementary metal-oxide-silicon (CMOS) field effect transistor (FET) devices comprising:

• providing a silicon semiconductor substrate of one polarity;
• forming within the silicon substrate an active device well, of opposite polarity, defined by field oxide dielectric isolation regions;
• forming over the silicon substrate active device region well silicon oxide gate oxide dielectric layers;
• forming over the silicon oxide gate oxide dielectric layers a patterned polycrystalline silicon gate electrode layer;
• thermally oxidizing the polycrystalline gate electrode layer and the silicon substrate to form a thicker silicon oxide dielectric layer at the edge and sides of the patterned polycrystalline silicon gate electrode layer and the silicon substrate regions beyond the gate electrode;
• forming spacers by etching back the silicon oxide dielectric layer beyond the edge of the patterned gate electrode layer;
• using spacers as a mask to implant ions to define shallow junction regions adjacent to the patterned gate electrode layer;
• and
• forming source and drain regions employing ion implantation using said spacers as a mask;
• wherein the anisotropic self-aligned etch process is a plasma process employing the following conditions:
• CF4 or CHF3 etching gasses;
• power from between about 100 to about 1000 watts;
• temperature from about 10 to about 200 degrees centigrade;
• and
• pressure from between about 1 to about 500 milliTorr.

A method for forming within a silicon semiconductor substrate employed within a microelectronics fabrication a field effect transistor (FET) device with attenuated drain leakage, short channel effect and punch-through leakage current comprising:

• providing a silicon semiconductor substrate;
• forming within the silicon semiconductor substrate field oxide isolation regions defining an active device region within said substrate;
• forming over the active region a silicon oxide gate oxide insulation layer;
• forming over the gate oxide insulation layer a patterned polycrystalline silicon layer which constitutes a gate electrode pattern;
• thermally oxidizing the silicon substrate and polycrystalline silicon gate electrode to form a thicker silicon oxide layer at the edge of the gate electrode and beyond;
• forming spacers by etching back by means of anisotropic self-aligned etching the thicker silicon oxide layer at the edge of the gate electrode and beyond;
• using said spacers as a mask to implant ions to define shallow source and drain extension regions;
• and
• forming source and drain regions employing ion implantation using said spacers as a mask;
• wherein the polycrystalline silicon gate electrode and the silicon substrate region beyond are thermally oxidized to form a silicon oxide layer whose thickness is about 70 angstroms.

A method for forming within a silicon semiconductor substrate, employed within an integrated circuit microelectronics fabrication, complementary metal-oxide-silicon (CMOS) field effect transistor (FET) devices comprising:

• providing a silicon semiconductor substrate of one polarity;
• forming within the silicon substrate an active device well, of opposite polarity, defined by field oxide dielectric isolation regions;
• forming over the silicon substrate active device region well silicon oxide gate oxide dielectric layers;
• forming over the silicon oxide gate oxide dielectric layers a patterned polycrystalline silicon gate electrode layer;
• thermally oxidizing the polycrystalline gate electrode layer and the silicon substrate to form a thicker silicon oxide dielectric layer at the edge and sides of the patterned polycrystalline silicon gate electrode layer and the silicon substrate regions beyond the gate electrode;
• forming spacers by etching back the silicon oxide dielectric layer beyond the edge of the patterned gate electrode layer;
• using said spacers as a mask to implant ions to define shallow junction regions adjacent to the patterned gate electrode layer;
• and
• forming source and drain regions employing ion implantation using said spacers as a mask;
• wherein the patterned polycrystalline silicon gate electrode layer and silicon substrate region beyond the gate electrode are thermally oxidized to form a silicon oxide dielectric layer whose thickness is about 70 angstroms.