US 6,548,362 B1Granted

Method of forming MOSFET with buried contact and air-gap gate structure

AssigneeTexas Instruments - Acer Incorporated

InventorShye-Lin Wu

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Abstract

A method of forming MOSFET with buried contacts and air-gap gate structure is disclosed. The method comprises following steps firstly, a gate is formed of pad oxide layer and a nitride layer sequentially on a silicon substrate, which has trench isolations. Then, a polysilicon layer and an oxide layer are deposited in order on all areas. Subsequently, an etched-back using the nitride layer a stopping layer is achieved. After that the nitride layer is removed thereby, forming a gate hollow region. After the pad oxide layer is removed, an oxynitride layer is regrown to be as the gate oxide. Thereafter, a silicon is deposited on all areas and refills in the gate hollow region. A planarization process is again performed using the oxide layer as an etch-stopping layer. Subsequently, the oxide layer is removed. S/D/G ion implanted into the polysilicon layer and the silicon layer. Then, the nitride spacers are removed to form dual recessed spaces. Another ion implantation is undertaken into first doped region and in a second doped region, which is in the bottom of the dual recessed spaces. A CVD oxide layer is then deposited on all areas and seals the dual recessed regions and forms the air-gaps. Finally an annealing process is carried out to form the shallow S/D, extended S/D junctions, and the buried contacts.

Claims20

Dependent claims

A method of forming MOSFET with buried contacts and air-gap gate structure, said method comprising the steps of:

providing a silicon substrate having trench isolations, thereby, defining an active region thereon;
forming a gate region on said active region, said gate region being formed sequentially by patterning a pad oxide layer and a nitride layer on said silicon substrate
forming a polysilicon layer on said gate region and elsewhere of said silicon substrate;
forming a first dielectric layer on said polysilicon layer;
etching back said first dielectric layer using said nitride layer of said gate region as an etch stopping layer;
removing said nitride layer of said gate region thereby, forming a gate hollow region;
forming nitride spacers on sidewaslls of said gate hollow region;
removing said pad oxide layer in said gate hollow region;
forming a gate dielectric layer on said gate hollow region;
depositing a silicon layer on all areas and refilled in said gate hollow region;
performing a planarization process using said first dielectric layer as an etch-stopping layer;
removing said first dielectric layer using said polysilicon layer as an etch-stopping layer;
performing a first ion implantation into all areas by conductive impurities to form first doped region in said polysilicon layer and said silicon layer;
removing said nitride spacers to form dual recessed spaces;
performing a second ion implantation into all areas by said conductive impurities in said first doped region and in a second doped region which is in bottom of said dual recessed spaces;
forming a second dielectric layer on all areas and sealing said dual recessed spaces to form air gaps in said dual recessed spaces;
and
annealing said silicon substrate so as to form source/drain junctions by driving said conductive impurities of said first doped region into said silicon substrate, and form extended source/drain junctions by driving said conductive impurities of said second doped region into said silicon substrate, said remnant polysilicon layer serving as said buried contact.

15 more elements

A method of forming MOSFET with buried contacts and air-gap gate structure, said method comprising the steps of:

providing a silicon substrate having trench isolations, thereby, defining an active region thereon;
forming a pad oxide layer on said active region and said trench isolations;
forming a nitride layer on said pad oxide layer;
forming a gate region on said active region by patterning said nitride layer and said pad oxide layer through a photoresist pattern and an anisotropic etching technique;
forming a polysilicon layer on said gate region and elsewhere of said silicon substrate;
forming a first oxide layer on said polysilicon layer;
etching back said first oxide layer using said nitride layer of said gate region as an etch stopping layer;
removing said nitride layer of said gate region thereby, forming a gate hollow region;
forming nitride spacers on sidewaslls of said gate hollow region;
removing said pad oxide layer of said gate hollow region;
forming a gate dielectric layer on said gate hollow region;
depositing a silicon layer on all areas and refilled in said gate hollow region;
performing a planarization process using said first oxide layer as an etch-stopping layer;
removing said first oxide layer using said polysilicon layer as an etch-stopping layer;
performing a first ion implantation into all areas by conductive impurities so that said polysilicon layer and said silicon layer contain said conductive impurities;
removing said nitride spacers to form recessed spaces;
performing a second ion implantation into all areas by said conductive impurities so that said polysilicon layer, said silicon layer, and said gate dielectric in said recessed space contain said conductive impurities;
forming a second oxide layer on all areas and sealing said recessed space to form air gaps in said recessed space;
and
annealing said silicon substrate so as to form source/drain junctions and said extended source/drain junctions by driving said conductive impurities into said silicon substrate, said remnant polysilicon layer serving as said buried contact.

17 more elements

Dependencies are inferred from the claim text.

Facts

Application: 09/325,811Filed 4 Jun 1999 · continuation in part
Priority: 22 May 1998
Granted: 15 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…
H10D 64/018
Manufacture or treatment: spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates