US 6,548,357 B2Granted

Modified gate processing for optimized definition of array and logic devices on same chip

AssigneesInternational Business Machines Corporation, Infineon Technologies AG

InventorsMary E. Weybright, Gary Bronner, Richard A. Conti, Ramachandra Divakaruni, Jeffrey Peter Gambino, Peter Hoh, Uwe Schroeder

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Abstract

Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

Claims18

Dependent claims

A method for defining gate conductors in both array and support device regions of a semiconductor integrated circuit, comprising:

(a) forming a gate conductor stack on a surface of a gate dielectric, said gate dielectric is formed on a surface of a semiconductor substrate having at least one array device region and at least one support device region;
(b) forming a first gate dielectric cap on at least the gate conductor stack in said at least one array device region;
(c) selectively patterning and etching the first gate dielectric cap in said at least one array device region, said first gate dielectric cap not being present in said at least one support device region after said etching;
(d) forming a second gate dielectric cap on all exposed surfaces in said at least one array device region and in said at least one support device region, said second gate dielectric cap being thinner than said first gate dielectric cap;
(e) selectively etching said second gate dielectric cap in said at least one array device region and in said at least one support device region, wherein said second etched gate dielectric cap in said at least one support device region serves as a gate conductor mask;
(f) block masking said support device region;
(g) etching exposed surfaces of said gate conductor stack in said at least one array device region stopping on said gate dielectric;
(h) depositing a barrier layer over at least said array device region;
(i) depositing a dielectric layer over said array device region and said support device region;
(j) depositing and patterning a photoresist to form patterning over said support device region while protecting said array device region;
and
(k) etching said gate conductor stack in said support device region.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/117,869Filed 8 Apr 2002 · division
Priority: 15 Nov 2000
Published: US 2002/0111025 A115 Aug 2002
Granted: 15 Apr 2003
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 12/09
Manufacture or treatment: with simultaneous manufacture of the peripheral circuit region and memory cells
H10D 84/0142
Manufacturing their gate conductors: the gate conductors having different shapes or dimensions
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs