Multi-layered gate for a CMOS imager
AssigneeMicron Technology, Inc.
InventorHoward E. Rhodes
Life of this patent
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Abstract
A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.
Claims26
A method of forming a multi-layered gate for use in an imaging device, comprising the steps of:
- forming a photosensitive region of a first conductivity type on a substrate;
- forming a first insulating layer over said substrate;
- forming a first conductive layer over said first insulating layer;
- forming a second insulating layer over said first conductive layer;
- forming a first gate by etching unmasked portions of said second insulating layer, and said first conductive layer to expose a surface of said first insulating layer;
- forming insulating sidewalls on lateral sides of said first gate;
- after forming said insulating sidewalls, removing exposed portions of said first insulating layer to expose a surface of said substrate;
- forming a fourth insulating over said exposed surface of said substrate;
- forming a second gate on said fourth insulating layer and at least one of said insulating sidewalls of said first gate, and such that said second gate overlaps a section of said first gate and is formed on said second insulating layer of said first gate, wherein at least one of said first or said second gate comprises a semi-transparent conductive layer.
Dependencies are inferred from the claim text.