Method of forming a storage node contact hole in a porous insulator layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChyi-Tsong Ni, Eric Su, Kevin Tsai
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Abstract
A process for increasing the surface area of a DRAM capacitor structure via definition of a capacitor in a porous insulator layer, wherein the porous insulator layer is comprised with voids, has been developed. The process features the use of an anisotropic dry etch procedure to form a capacitor opening in a porous insulator layer, exposing a portion of the voids located on the sides of the capacitor opening extending into the porous insulator layer. An isotropic wet etch is then used to enlarge the surface area of the exposed voids, allowing the surface area for a subsequently formed, overlying storage node structure, to be increased.
Claims10
A method of forming a capacitor structure for a DRAM device featuring a capacitor opening defined in a porous insulator layer, then subjected to a wet etch procedure to form grooves in the sides of said capacitor opening, to increase the surface area for a subsequently formed capacitor structure, comprising the steps of:
- providing transfer gate transistor structures, comprised of word line structures, with source/drain regions located in a region of said semiconductor substrate not covered by said word line structures, and providing storage node plugs, overlying and contacting said source/drain regions;
- depositing said porous insulator layer, with said porous insulator layer comprised containing voids;
- performing a first anisotropic dry etch procedure to define a first capacitor opening in said porous insulator layer, exposing top surface of a storage node plug structure, and with said first capacitor opening exposing a portion of said voids in said porous insulator layer, located on the sides of said first capacitor opening;
- performing said wet etch procedure resulting in formation of a second capacitor opening, featuring grooves in sides of said second capacitor opening, with said grooves formed from said portion of voids, and with said grooves extending from sides of said second capacitor layer into said porous insulator layer;
- depositing a first polysilicon layer, coating all exposed surfaces of said second capacitor opening;
- forming a capacitor dielectric layer on said first polysilicon layer;
- depositing a second polysilicon layer;
- and
- performing a second anisotropic dry etch procedure to form said capacitor structure, incorporating definition of a capacitor top plate structure from said second polysilicon layer, definition of a capacitor dielectric component, and definition of a storage node structure from said first polysilicon layer, with said storage node structure located in said second capacitor opening, wherein said second capacitor opening is comprised with said grooves extending from sides of said second capacitor opening into said porous insulator layer.
Dependencies are inferred from the claim text.