US 6,548,338 B2 · Integrated high-performance decoupling capacitor and heat sink

Abstract

A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip. The structure thus provides both a significant and effective decoupling capacitance in close proximity to the active circuit on the chip requiring such decoupling capacitance as well as providing improved heat sinking for the decoupled active circuit.

Claims7

Dependent claims

A process of forming a capacitor on a semiconductor device comprising the steps of:

selecting a silicon on insulator semiconductor body formed of an epitaxial layer and a substrate layer separated by a buried oxide layer, said epitaxial layer forming a first major surface of said body and said substrate layer forming a second major surface of said body;
forming an integrated circuit, comprised of a plurality of active and passive devices, in said epitaxial layer;
forming a plurality of wiring levels on said first surface and overlying said integrated circuit;
coupling selected ones of said wiring levels to selected ones of said active and passive devices;
forming trenches in said second surface of said semiconductor body;
forming a first insulating layer on said second surface of said semiconductor body;
forming a layer of refractory material selected from the class consisting of tantalum, tantalum nitride tungsten and tungsten nitride on said first insulating layer;
forming a conductive layer on said layer of refractory material;
forming a second insulating layer on said conductive layer;
forming conductive means between said a first one of said wiring levels and said substrate layer;
and
forming conductive means between a second one of said wiring levels and said conductive layer;
whereby said conductive layer forms one plate of a capacitor with respect to said substrate which forms the second plate of said capacitor.

10 more elements

A process of forming a castellated decoupling capacitor on a semiconductor comprising the steps of:

selecting a semiconductor substrate having first and second major surfaces,
depositing a silicon dioxide layer on said first surface;
depositing a first layer of refractory material, approximately 50 Å, of tantalum nitride (TaN) on said silicon dioxide layer;
depositing a layer of tantalum, less than 1000 Å in thickness, on said first layer of refractory material;
depositing a layer of a conductive metal, greater than 20 microns, over said first layer of refractory material;
reactively ion etching a plurality of grooves, each groove being separated from an adjacent groove by a fin in said layer of conductive metal;
coating the surface of each of said grooves and each separating fin with a second layer layer of a refractory material;
forming a dielectric layer, less than 1000 Å in thickness, in said plurality of grooves and over each separating fin;
forming a second layer of a refractory material on said dielectric layer in said plurality of grooves and over each separating fin;
forming a second deposit, 20 microns, of a conductive metal over said second layer of a refractory material;
forming an integrated circuit, comprised of a plurality of active and passive devices, in said second surface;
forming a plurality of wiring levels on said first surface over said plurality of active and passive devices;
coupling said wiring levels to said active and passive devices in said integrated circuit;
forming a dielectric layer on said second major surface of said substrate;
depositing a first conductive material on said dielectric layer on said second major surface of said substrate;
forming a first hole through said wiring levels and said first region into said second region;
terminating said first hole in said second region;
forming a second hole through said wiring levels, said first and second regions and said dielectric level on said second major surface to said first conductive material;
forming a dielectric lining on the walls of said first and second holes;
depositing a second conductive material on the dielectric lining in said first and second holes;
said second conductive material on the dielectric lining in said first hole extending though said first hole to electrically connect a first selected wiring level on said integrated circuit to said second region, and said second conductive layer in said second hole extending though said second hole to electrically connect a second selected wiring level on said integrated circuit to contact said first conductive material deposited on said dielectric layer on said second major surface of said substrate to form a capacitor between said second region in said substrate and said first conductive material on said dielectric layer on said second major surface of said substrate.

18 more elements

A process of forming a capacitor with heat sinking capacity on a semiconductor substrate having first and second major surfaces comprising the steps of:

selecting a semiconductor substrate having first and second major surfaces and a buried oxide layer in said substrate substantially parallel to and between said first and second major surfaces to define first and second regions in said substrate;
forming a plurality of trenches in said second region;
forming an integrated circuit, comprised of a plurality of active and passive devices, in said first region;
forming a plurality of insulated wiring levels on said first surface, and coupling respective ones of said wiring levels to respective ones of said active and passive devices;
forming a first dielectric layer on said formed second major surface of said substrate;
depositing a first metallic layer on said first dielectric layer on said second major surface of said substrate;
forming a first via through said first region, said buried oxide layer, said second region and said first dielectric layer to said first metallic layer;
forming a second via through said first region, said buried oxide layer, and terminating said second via in said second region;
forming a dielectric lining on the walls of said first and second vias;
forming a first conductive path in said first via to electrically contact said second region and said first metallic layer to said integrated circuit and a second conductive path in said second via to respectively electrically contact said second region and said first metallic layer to said integrated circuit;
forming a second dielectric layer on said first conductive layer on second major surface of said substrate and said second dielectric lining extending down the wall of said second through hole, said second dielectric lining in said second through hole extending to said selected region of said integrated circuit;
and
depositing a second conductive layer on said second dielectric layer on said second major surface of said substrate and on said second dielectric lining in said second hole;
said second conductive layer coating said second dielectric in said second hole being substantially coaxial with said wall of said second hole and extending though said second hole and electrically contacting said second selected region of said integrated circuit whereby said first and second conductive layers form a respective plate of a respective capacitor with respect to said substrate which is connected to ground and forms the second plate of each respective capacitor.

11 more elements

Dependencies are inferred from the claim text.

Integrated high-performance decoupling capacitor and heat sink

Life of this patent

Integrated high-performance decoupling capacitor and heat sink

Life of this patent

Abstract

Claims7