Planarization of a polysilicon layer surface by chemical mechanical polish to improve lithography and silicide formation

A method of fabricating a circuit device having a substrate, comprising the steps of:

• a. forming a plurality of shallow trench isolation regions in the substrate, wherein each shallow trench isolation region has a portion of a side surface that extends above an adjacent substrate surface,
• b. forming a first conductive layer over the substrate and over at least a portion of two opposing side surfaces of corresponding shallow trench isolation,
• c. forming an interpoly dielectric layer upon the first conductive layer,
• d. forming a second conductive layer upon the interpoly dielectric layer, and
• e. removing a portion of the second conductive layer so as to approximately smooth an upper surface of the second conductive layer.

A method of fabricating a circuit device having a substrate, comprising:

• a. forming the first conductive layer over the substrate and over at least a portion of two opposing side surfaces of corresponding shallow trench isolation regions, so that a channel portion is formed in the first conductive layer,
• b. forming a plurality of shallow trench isolation regions in the substrate, wherein each shallow trench isolation region has a portion of a side surface that extends above an adjacent substrate surface,
• c. forming the interpoly dielectric layer upon the first conductive layer, including the channel portion;
• d. forming the second conductive layer upon the interpoly dielectric layer, including the portion of the interpoly dielectric layer covering the channel portion;
• and
• e. removing a portion of the second conductive layer so as to approximately planarize an upper surface of the second conductive layer.

A method of fabricating a circuit device having a substrate, comprising:

• a. forming a plurality of shallow trench isolation regions in the substrate, wherein each shallow trench isolation region has a portion of a side surface that extends above an adjacent substrate surface;
• b. forming a tunnel oxide layer that further comprises a portion of the substrate;
• c. forming a first conductive layer over the substrate and over at least a portion of two opposing side surfaces of corresponding shallow trench isolation, wherein the tunnel oxide layer is sandwiched between at least a portion of the substrate and at least a portion of the first conductive layer, and wherein each shallow trench isolation region has a portion of a side surface that extends above an adjacent tunnel oxide layer top surface;
• d. forming an interpoly dielectric layer upon the first conductive layer;
• e. forming a second conductive layer upon the interpoly dielectric layer;
• and
• f. removing a portion of the second conductive layer so as to approximately smooth