Method for fabricating thin film transistor including crystalline silicon active layer

#The present invention relates to a TFT used for liquid crystal display (LCD) and organic light emitting diode (OLED), etc. More particularly, the present invention relates to a TFT including a crystalline silicon active layer providing the source, drain, and channel regions of the TFT, and to a method for fabricating a TFT including the crystalline silicon active layer.

#Thin film transistor (TFTs) used for display devices such as liquid crystal display (LCD) and organic light emitting diode (OLED) is formed by depositing a silicon layer on a transparent substrate such as a glass or quartz, forming a gate and a gate electrode on the silicon layer, implanting dopant in the source and the drain regions of the silicon layer, performing an annealing to activate the dopant, and finally forming an insulation layer thereon. An active layer constituting the source, drain, and channel regions of a TFT is formed by depositing a silicon layer on a transparent substrate such as glass by means of chemical vapor deposition (CVD) and the like. The silicon layer directly deposited on the substrate by CVD is an amorphous silicon layer, which has low electron mobility. As display devices using thin film transistors requires high operation speed and miniaturized structure, the integration degree of its driving ICs becomes higher and the aperture ratio of the pixel region becomes lower. Therefore, it is required increase the electron mobility of the silicon layer in order to form the driving circuit concurrently with the pixel TFT and to enhance the pixel aperture ratio. For this purpose, technologies for forming a polycrystalline silicon layer having high electron mobility by crystallizing an amorphous silicon layer with thermal treatment have been in use as described below.

#Solid phase crystallization (SPC) method is used to anneal an amorphous silicon layer at a temperature of 600° C. or below for a few hours or tens of hours. 600° C. is the temperature causing deformation of the glass constituting the substrate. However, the SPC method has the following disadvantages. Since the SPC method requires a thermal treatment for a long time, the SPC method has low productivity. In addition, when annealing a large-sized substrate, the SPC method causes deformation of the substrate during the extended thermal treatment even at a temperature of 600° C. or below.

#The embodiments of the present invention will be explained with reference to the accompanying drawings, in which:

#FIG. 1A to FIG. 1D are cross-sectional views illustrating the sequence of prior method for fabricating a crystalline silicon TFT by using MIC and MILC;

#FIG. 2A to FIG. 2E are cross-sectional illustrating the sequence of another prior method for fabricating a crystalline silicon TFT having a lightly doped drain (LDD) region;

#Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

#FIG. 3A to FIG. 3F are cross-sectional views illustrating the sequence of a method for fabricating a crystalline silicon TFT by using the MILC according to a first embodiment of the present invention. Referring to FIG. 3A, an amorphous silicon layer 31 to form an active layer of a TFT is formed and patterned on an insulation substrate 30. A gate insulation layer 32, a lower gate electrode 33, and an upper gate electrode 34 are formed on the amorphous silicon layer 31. Referring to FIG. 3B, a high-density impurity is doped in the amorphous silicon layer 31 by using the gate electrode 34 as a mask, thereby forming a source region 31S and a drain region 31D. When fabricating an NMOS (N-channel metal oxide semiconductor) TFT, the silicon layer 31 is doped with a dopant such as PH3, P and As with a dose of 1E14-1E22/cm3 (preferably 1E15-1E21/cm3) at an energy level of 10-200 KeV (preferably 30-100 KeV) by using ion shower doping method, ion implantation method, or another ion implantation methods in the process of FIG. 3B. On the other hand, when fabricating a PMOS (P-channel metal oxide semiconductor), the silicon layer 31 is doped with a dopant such as B2H6, B and BH3 with a dose of 1E13-1E22/cm3 (preferably 1E14˜1E21/cm3) at an energy level of 20-70 KeV in the process of FIG. 3B.

#Then, as shown in FIG. 3C, a metal layer 35 such as Ni inducing crystallization of the amorphous silicon layer 31 is formed on the amorphous silicon layer 31 and the substrate 30 using the gate electrode 34 as a mask. As the metal for inducing the crystallization of the amorphous silicon layer, Ni or Pd is preferably used, but other metals such as Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd and Pt or the material containing at least one of these metals also can be used to form the metal layer 35. The crystallization inducing metal such as Ni, Pd is applied on the silicon layer by sputtering, heating evaporation, PECVD (plasma enhanced chemical vapor deposition), solution coating or ion implantation. However, sputtering method is preferably used to form the metal layer 35. The thickness of the metal layer 35 may be selected within a range in which the crystallization of the amorphous silicon layer 31 is properly induced. The metal layer 35 is formed with a thickness of about 1 Å to 10,000 Å. Preferably, the metal layer 35 is formed with a thickness of about 10 Å to 200 Å. If the width of the upper gate electrode 34 is wider than that of the lower gate electrode 33, the crystallization inducing metal layer is not formed in the portion of the silicon layer indicated with 31LDD, where an LDD region is formed. Thus, the crystallization inducing metal is offset from the channel region 31C by a predetermined distance. If the channel region is directly in contact with the crystallization inducing metal without a metal offset region between the channel region 31C and the metal layer 35, the metal component used to induce the crystallization of the silicon layer resides in the channel region after crystallization of the silicon layer. Then, the residual metal component deteriorates the characteristics of the transistor. In the present invention, the width of the metal offset region between the crystallization inducing metal and the channel region, which is to form the LDD region 31LDD later, is set within a range of 100 Ř20,000 Å. Preferably, the width of the metal offset region is set within a range of 5,000 Ř20,000 Å. In the present invention, the order of the high density doping process and the MIC metal forming process may be switched without affecting the effects of the present invention.