Wafer thickness compensation for interchip planarity

In an integrated circuit package, including a carrier, said carrier having a topography of mesas projected from a surface, said mesas having inwardly sloping sides, and individual semiconductor circuit chips, each said chip having a device side surface and an opposite bottom surface, said bottom surface having a conversely matching topography to permit self-aligned positioning of each said chip on said carrier, a method for compensating for variations in chip thickness in order to place said device side surfaces of said chips in the same plane, comprising the steps of:

• measuring the thickness of said individual circuit chips, and determining for each said chip a thickness offset which is the difference between a reference thickness and said measured chip thickness, said reference thickness being equal to or greater than the thickness of the thickest of said individual chips;
• and
• controlling the width of recesses in said bottom surface topography so that, for each said individual circuit chip, alignment on the respective projections of said carrier surface will elevate said respective bottom chip surface above said carrier surface by an amount equal to said respective thickness offset.