US 6,547,875 B1 · Epitaxial wafer and a method for manufacturing the same

Abstract

A wafer of the invention is a silicon wafer of 0.02 Ωcm or less in resistivity for deposition of an epitaxial layer, and the number of crystal originated particles (COP) and the number of interstitial-type large dislocation loops (L/D) are respectively 0 to 10 per wafer. A wafer of the invention is an epitaxial wafer having an epitaxial layer being 0.1 Ωcm or more in resistivity and 0.5 to 5 μm in thickness formed on this wafer by means of a CVD method. A wafer of the invention is OSF-free and hardly makes traces of COP and L/D appear on the surface of an epitaxial layer when the epitaxial layer is formed. By heat treatment in a semiconductor device manufacturing process after the epitaxial layer is formed, BMDs occur uniformly and highly in density in the wafer and a uniform IG effect can be obtained in the wafer.

Claims4

Dependent claims

An epitaxial wafer manufacturing method comprising the steps of:

pulling a single silicon ingot,
making a silicon wafer by slicing said silicon ingot, and
forming a single silicon crystal epitaxial layer on said silicon wafer by means of a chemical vapor deposition method,
wherein on the assumption that a pulling speed is V (mm/minute) and a temperature gradient in an axial direction in the center of said ingot is Ga (° C./mm) and a temperature gradient in the axial direction in the periphery of said ingot is Gb (° C./mm) in a temperature range from the melting point of silicon to 1300° C., said ingot is pulled so that V/Ga and V/Gb are respectively 0.23 to 0.50 mm2/minute° C., and the epitaxial layer is formed with 0.2 to 5 μm in thickness on the surface of the silicon wafer.

1 more element

Dependencies are inferred from the claim text.

Epitaxial wafer and a method for manufacturing the same

Life of this patent

Epitaxial wafer and a method for manufacturing the same

Life of this patent

Abstract

Claims4