Latching serial data in an ink jet print head

An ink jet print head for printing an image on a print medium, the print head comprising:

• a plurality of ink droplet generators for ejecting droplets of ink onto a print medium based at least in part upon selection signals;
• at least N−1 number of selection lines coupled to one or more of the ink droplet generators, the selection lines for carrying the selection signals;
• a serial data input line for receiving serial data describing the image to be printed on the print medium, where the serial data includes at least N number of serial data bits in a data segment;
• a clock line for receiving a clock signal;
• an N-bit serial shift register including:
• a first single-bit storage register having:
• a first-register data input coupled to the serial input data line;
• a first-register data output;
• and
• a first-register clock input coupled to the clock line;
• an Nth single-bit storage register having:
• an Nth-register data input;
• an Nth-register data output;
• and
• an Nth-register clock input coupled to the clock line;
• and
• N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers;
• a first buffer circuit having an input and an output, the input of the first buffer circuit connected to the Nth register data output;
• N−1 number of data latches having:
• data-latch inputs coupled to the data outputs of the first single-bit storage register and the N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers;
• data-latch outputs coupled to N−1 number of selection lines;
• and
• data-latch clock inputs coupled to the output of the first buffer circuit,
• a clear input line;
• a logic circuit having a first input connected to the clear input line, a second input connected to the output of the first buffer circuit, and a logic circuit output;
• the N−1 number of data latches each including a data-latch clear input coupled to the clear input line;
• and
• the single-bit storage registers of the N-bit serial shift register each including a storage register clear input coupled to the logic circuit output,
• where a bit provided from the Nth-register data output, through the first buffer circuit, and to the data-latch clock inputs causes at least some of the other serial data bits in the first and the N−2 number of single-bit storage registers to be transferred from their data outputs to the data-latch inputs of corresponding ones of the N−1 number of data latches, the first buffer circuit providing a time delay between the Nth-register data output and the data-latch clock inputs.

A method for providing print data to an ink droplet generator addressing circuit in an ink jet print head based on serial input data, the method comprising:

• (a) shifting N−1 of N number of bits of the serial input data into an N-bit serial shift register, where a first bit of the N number of bits that is shifted into the shift register is a load trigger bit;
• (b) shifting an Nth bit of the N number of bits into the shift register, thereby causing the load trigger bit to be shifted into an Nth register of the shift register;
• (c) after a predetermined time delay, providing the load trigger bit from the Nth register of the shift register to clock inputs of N−1 number of data latches;
• (d) loading the N−1 number of data latches with the N−1 number of bits of data residing in the shift register when the load trigger bit is provided to the clock inputs of the data latches;
• (e) providing the N−1 number of bits of data from the N−1 number of data latches to the ink droplet generator addressing circuit;
• (f) after a predetermined time delay, providing the load trigger bit from the Nth register of the shift register to a trigger input of a logic circuit;
• (g) providing a clear bit to a clear input of the logic circuit;
• and
• (h) upon the occurrence steps (f) and (g), providing a clear signal from an output of the logic circuit to the N-bit serial shift register, thereby clearing the N bits of the N-bit serial shift register.

A print data loading circuit for receiving at least N bits of serial data on a serial input data line, at least some of the bits of serial data describing an image to be formed on a print medium by a printing device, the loading circuit for providing the print data to a data bus in an addressing circuit, where the addressing circuit addresses one or more image-forming elements in the printing device, the circuit comprising:

• an N-bit serial shift register including:
• a first single-bit storage register having:
• a first-register data input coupled to the serial input data line;
• a first-register data output;
• and
• a first-register clock input coupled to a clock line;
• an Nth single-bit storage register having:
• an Nth-register data input;
• an Nth-register data output;
• and
• an Nth-register clock input coupled to the clock line;
• and
• N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers, each having a data input and a data output;
• N−1 number of data latches having:
• data-latch inputs coupled to the data outputs of the first single-bit storage register and the N−2 number of single-bit storage registers serially coupled between the first and Nth single-bit storage registers;
• data-latch outputs coupled to N−1 number of selection lines that are coupled to the data bus;
• and
• data-latch clock inputs coupled to the Nth register data output,
• a clear input line;
• a logic circuit having a first input connected to the clear input line, a second input connected to the Nth register data output, and a logic circuit output;
• the N−1 number of data latches each including a data-latch clear input coupled to the clear input line;
• and
• the single-bit storage registers of the N-bit serial shift register each including a storage register clear input coupled to the logic circuit output,
• where a bit provided from the Nth-register data output to the data-latch clock inputs causes at least some of the other data bits in the first and the N−2 number of single-bit storage registers to be transferred from their data outputs to the data-latch inputs of corresponding ones of the N−1 number of data latches.