Thermal ink jet printhead system with multiple output driver circuit for powering heating element and associated method

A thermal ink jet printhead comprising:

• a base member having a plurality of ink flow channels that communicate with an ink reservoir and terminate in a nozzle through which ink is expelled in which the base member is part of a thermal ink jet printhead;
• a plurality of heating elements, each ink flow channel having a corresponding one of said heating elements connected thereto;
• a monolithically integrated multiple output driver circuit formed as a semiconductor integrated circuit and connected to the thermal ink jet printhead, said multiple output driver circuit further comprising:
• a plurality of power output transistors Q1, Q2 . . . QX and gate driver circuits each formed as a push/pull transistor driver circuit, each power output transistor Q1, Q2 . . . QX connected to a corresponding one of a push/pull transistor driver circuit, wherein a power output transistor and push/pull transistor driver circuit are connected to a corresponding one heating element;
• a single closed loop reference circuit operatively connected to each of said push/pull transistor drive circuits in an open loop configuration, said closed loop reference circuit including only one reference transistor having a gate, only one push/pull transistor driver circuit having a gate, source and drain and connected to said gate of said reference transistor, and only one reference amplifier that receives as inputs a reference voltage from the reference transistor and a source of current and including an amplifier output operatively connected to each of said push/pull transistor driver circuits of said power output transistors and to one of either the source or drain of said push/pull transistor driver circuit of said reference transistor, wherein the reference amplifier regulates the reference transistor directly and the power output transistors by matching;
• and
• a logic circuit and controller operatively connected to the gate driver circuits and power output transistors Q1, Q2 . . . QX to provide logic pulses for turning on and off each power MOS transistor Q1, Q2 . . . QX via an associated push/pull transistor driver circuit.

A multiple output driver circuit formed as a semiconductor integrated circuit comprising:

• a semiconductor substrate;
• a plurality of power MOS transistors Q1, Q2 . . . QX and gate drive circuits each formed as push/pull transistor driver circuits and formed on the semiconductor substrate, each power output transistor Q1, Q2 . . . QX connected to a corresponding one of a push/pull transistor driver circuit, and each power MOS transistor Q1, Q2 . . . QX and push/pull transistor driver circuit adapted to be respectively connected to a respective load;
• a single closed loop reference circuit formed on the semiconductor substrate and operatively connected to each push/pull transistor driver circuit of each power MOS transistor in open loop configuration, said reference circuit including only one reference transistor and an associated push/pull transistor driver circuit having a gate, source and drain, and only one reference amplifier that receives as inputs a reference voltage from the reference transistor and a source of current, and an amplifier output operatively connected to said push/pull transistor driver circuits of said power MOS transistors and either one of the source or drain of said push/pull transistor driver circuit of said reference transistor, wherein the reference amplifier regulates the reference transistor directly and the power MOS transistors by matching;
• and
• a logic circuit and controller operatively connected to the gate driver circuits and power output transistors Q1, Q2 . . . QX to provide logic pulses for turning on and off each power MOS transistor Q1, Q2 . . . QX via an associated push/pull transistor driver circuit.