Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein

A multi-port cache memory device, comprising:

• a data input register having an input electrically coupled to a first input port of the cache memory device;
• a multiplexer responsive to a direct path select signal and a memory path select signal, said multiplexer having a first input electrically coupled to an output of said data input register, and a second input electrically coupled by a pass gate device to a second bidirectional port of the cache memory device;
• and
• an output register having an input electrically coupled to an output of said multiplexer and an output electrically coupled to a third output port of the cache memory device.

A multi-port cache memory device, comprising:

• a data input register having an input electrically coupled to a first port of the cache memory device;
• a multiplexer responsive to a direct path select signal and a memory path select signal, said multiplexer having a first input electrically coupled to an output of said data input register and a second input electrically coupled to a second port of the cache memory device;
• and
• an output register having a data input electrically coupled to an output of said multiplexer, an address input that is configured to receive a read address and an output electrically coupled to a third port of the cache memory device;
• wherein said output register generates a complementary data input signal and a complementary read address;
• wherein said output register comprises first and second NMOS pull-down transistors connected in parallel and first and second PMOS pull-up transistors connected in parallel;
• wherein the first NMOS pull-down transistor and the first PMOS pull-up transistor are responsive to the complementary data input signal;
• and wherein the second NMOS pull-down transistor and the second PMOS pull-up transistor are responsive to the complementary read address and the read address, respectively.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array having a write port and a read port;
• and
• a quad-port cache memory device having a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port of said embedded memory array and a second embedded memory port that is electrically coupled to the read port of said embedded memory array, said quad-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the undirectional data input port and a data output electrically coupled to the first embedded memory port;
• a retransmit register that is responsive to a retransmit address and has a data input electrically coupled to the unidirectional data input port;
• a multiplexer that is responsive to at least one path select signal and has a first input electrically coupled to the data output of said data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of said retransmit register;
• and
• a data output register that is responsive to a read address and has a data input electrically coupled to an output of said multiplexer and a data output electrically coupled to the unidirectional data output port.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array having a write port and a read port;
• and
• a quad-port cache memory device having a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the write port of said embedded memory array and a second embedded memory port that is electrically coupled to the read port of said embedded memory array, said quad-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the unidirectional data input port and a data output electrically coupled to the first embedded memory port;
• a retransmit register that is responsive to a retransmit address and has a data input electrically coupled to the undirectional data input port;
• a multiplexer that is responsive to at least one path select signal and has a first input electrically coupled to the data output of said data input register, a second input electrically coupled to the second embedded memory port and a third input electrically coupled to a data output of said retransmit register;
• a data output register that is responsive to a read address and has a data input electrically coupled to an output of said multiplexer and a data output electrically coupled to the unidirectional data output port;
• and
• a retransmit-from-mark register having a data input electrically coupled to the data output port and a data output electrically coupled to a fourth input of said multiplexer.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array;
• and
• a multi-port cache memory device having a unidirectional data input port, a unidirectional data output port and an embedded memory port that is electrically coupled to said embedded memory array, said multi-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the unidirectional data input port;
• a retransmit register that is responsive to a retransmit address and has a data input electrically coupled to the unidirectional data input port;
• a multiplexer that is responsive to at least one path select signal and has a first input electrically coupled to a data output of said data input register, a second input electrically coupled to the embedded memory port and a third input electrically coupled to a data output of said retransmit register;
• and
• a data output register that is responsive to a read address and has a data input electrically coupled to an output of said multiplexer and a data output electrically coupled to the undirectional data output port.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array;
• and
• a multi-port cache memory device having a unidirectional data input port, a unidirectional data output port and a first embedded memory port that is electrically coupled to said embedded memory array, said multi-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the unidirectional data input port;
• a retransmit register that is responsive to a retransmit address and has a data input electrically coupled to the unidirectional data input port;
• a data output register that is responsive to a read address and has a data output electrically coupled to the unidirectional data output port;
• and
• means, responsive to at least one path select signal, for selectively routing data one-at-a-time from either said data input register, said retransmit register or the first embedded memory port, to said data output register.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array;
• and
• a multi-port cache memory device having a unidirectional data input port, a unidirectional data output port and a first embedded memory port that is electrically coupled to said embedded memory array, said multi-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the unidirectional data input port;
• a retransmit register that is responsive to a retransmit address and has a data input electrically coupled to the unidirectional data input port;
• a data output register that is responsive to a read address and has a data output electrically coupled to the unidirectional data output port;
• a retransmit-from-mark register having a data input electrically coupled to the unidirectional data output port;
• and
• means, responsive to at least one path select signal, for selectively routing data one-at-a-time from either said data input register, said retransmit register, said retransmit-from-mark register or the first embedded memory port, to said data output register.

A first-in first-out (FIFO) memory device, comprising:

• an embedded memory array having a write port and a read port;
• and
• a quad-port cache memory device having a unidirectional data input port, a unidirectional data output port, a first embedded memory port that is electrically coupled to the read port of said embedded memory array and a second embedded memory port that is electrically coupled to a write port of said embedded memory array, said quad-port cache memory device comprising:
• a data input register that is responsive to a write address and has a data input electrically coupled to the unidirectional data input port and a data output electrically coupled to the second embedded memory port;
• a data output register that is responsive to a read address and has a data output electrically coupled to the unidirectional data output port;
• and
• means, responsive to at least one path select signal, for selectively routing data one-at-a-time from either said data input register or the first embedded memory port, to said data output register.