US 6,545,904 B2 · 6F2 DRAM ARRAY, A DRAM ARRAY FORMED ON A SEMICONDUCTIVE SUBSTRATE, A METHOD OF FORMING MEMORY CELLS IN A 6F2 DRAM ARRAY AND A METHOD OF ISOLATING A SINGLE ROW OF MEMORY CELLS IN A 6F2 DRAM ARRAY

Abstract

The present invention includes a 6F2 DRAM array formed on a semiconductor substrate. The memory array includes a first memory cell. The first memory cell includes a first access transistor and a first data storage capacitor. A first load electrode of the first access transistor is coupled to the first data storage capacitor via a first storage node formed on the substrate. The memory array also includes a second memory cell. The second memory cell includes a second access transistor and a second data storage capacitor. A first load electrode of the second access transistor is coupled to the second data storage capacitor via a second storage node formed on the substrate. The first and second access transistors have a gate dielectric having a first thickness. The memory array further includes an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween. The isolation gate has a gate dielectric having a second thickness that is greater than the first thickness. The isolation gate dielectric may extend above or below a surface of the substrate.

Claims43

Dependent claims

A 6F2 DRAM array including:

a first memory cell including a first access transistor and a first data storage capacitor, a first load electrode of the first access transistor being coupled to the first data storage capacitor via a first storage node formed on a substrate;
a second memory cell including a second access transistor and a second data storage capacitor, a first load electrode of the second access transistor being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access transistors each including a first gate dielectric with a first thickness;
and
an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate including a second gate dielectric comprising an isolation gate dielectric with a second thickness that is greater than the first thickness used in at least the access transistors.

1 more element

A DRAM array formed on a semiconductive substrate and including:

a first memory cell including a first access device and a first data storage capacitor, a first load electrode of the first access device being coupled to the first data storage capacitor via a first storage node formed on the substrate;
a second memory cell including a second access device and a second data storage capacitor, a first load electrode of the second access device being coupled to the second data storage capacitor via a second storage node formed on the substrate, the first and second access devices having a first threshold voltage;
and
an isolation gate formed between the first and second storage nodes and configured to provide electrical isolation therebetween, the isolation gate having a second threshold voltage that is greater than the first threshold voltage.

1 more element

Dependencies are inferred from the claim text.

6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array

Life of this patent

6f2 dram array, a dram array formed on a semiconductive substrate, a method of forming memory cells in a 6f2 dram array and a method of isolating a single row of memory cells in a 6f2 dram array

Life of this patent

Abstract

Claims43