Rail-to-rail class AB output stage for operational amplifier with wide supply range

A method of reducing impact ionization in an N-channel MOSFET in a CMOS integrated circuit device so as to reduce drain-to-body leakage current in the MOSFET, comprising the steps of:

• (a) forming the MOSFET in a P-type substrate in a single-well CMOS structure by using a single-well CMOS manufacturing process;
• (b) coupling a first input of an amplifier to a drain of the MOSFET, and coupling a second input of the amplifier to a voltage source;
• and
• (c) operating the amplifier to control a drain current in the MOSFET so as to prevent the magnitude of the drain-source voltage of the MOSFET from exceeding a value at which impact ionization causes the drain-to-body leakage current to exceed a predetermined level.

An impact ionization reduction circuit in a CMOS integrated circuit made by using a single-well CMOS manufacturing process, the impact ionization reduction circuit comprising:

• (a) an N-channel MOSFET formed in a P-type substrate of the CMOS integrated circuit;
• (b) a amplifier having a first input coupled to a drain of the N-channel MOSFET and a second input coupled to a voltage having a fixed relationship to a voltage of the source of the N-channel MOSFET;
• and
• (c) circuitry operative in conjunction with the amplifier to control the drain current of the N-channel MOSFET so as to prevent the magnitude of the drain-source voltage of the N-channel MOSFET from exceeding a value at which impact ionization causes the drain-to-body leakage current in the N-channel MOSFET to exceed a predetermined level.

A rail-to-rail class AB output stage including:

• (a) a P-channel pull-up transistor having a first terminal coupled to a first supply rail voltage, a gate coupled to a first input conductor of the output stage, and a second terminal coupled to an output terminal of the output stage;
• (b) an N-channel pull-down transistor having a first terminal coupled to a second supply rail voltage, a gate coupled to a second input conductor of the output stage, and a second terminal coupled to the output terminal;
• (c) a P-channel first bias transistor having a source coupled to the first input conductor;
• (d) an N-channel second bias transistor having a source coupled to the second input terminal and a drain connected to a drain of the first bias transistor;
• (e) a amplifier having an output coupled to a gate of the first bias transistor, a first input coupled to the drain of the second bias transistor, and a second input coupled to a first reference voltage;
• and
• (f) a voltage source connected to the gate of the second bias transistor.

A rail-to-rail class AB output stage including:

• (a) a P-channel pull-up transistor having a source coupled to a first supply rail voltage, a gate coupled to a first input conductor of the output stage, and a drain coupled to an output terminal of the output stage;
• (b) an N-channel pull-down transistor having a source coupled to a second supply rail voltage, a gate coupled to a second input conductor of the output stage, and a drain coupled to the output terminal;
• (c) a P-channel first bias transistor having a source coupled to the first input conductor;
• (d) an N-channel second bias transistor having a source coupled to the second input terminal and a drain connected to a drain of the first bias transistor;
• (e) a amplifier having an output coupled to a gate of the first bias transistor, a first input coupled to the drain of the second bias transistor, and a second input coupled to a first reference voltage;
• and
• (f) a voltage source connected to the gate of the second bias transistor.

A rail-to-rail class AB output stage including:

• (a) a P-channel pull-up transistor having a source coupled to a first supply rail voltage, a gate coupled to a first input conductor of the output stage, and a drain coupled to an output terminal of the output stage;
• (b) an N-channel pull-down transistor having a source coupled to a second supply rail voltage, a gate coupled to a second input conductor of the output stage, and a drain coupled to the output terminal;
• (c) a P-channel first bias transistor having a source coupled to the first input conductor, a drain coupled to the second input conductor, and a gate coupled to a first reference voltage;
• (d) a first bias circuit coupled between the first and second supply rail voltages and producing a first bias voltage on a gate of the first bias transistor;
• (e) a P-channel second bias transistor having a source coupled to be first input conductor;
• (f) an N-channel third bias transistor having a source coupled to the second input terminal and a drain connected to a drain of the second bias transistor;
• (g) a amplifier having an output coupled to a gate of the second bias transistor, a non-inverting input coupled to the drain of the third bias transistor, and an inverting input coupled to a second reference voltage;
• and
• (h) a second bias circuit coupled between the first and second supply rail voltages and producing a third bias voltage on the gate of the third bias transistor.

A CMOS rail-to-rail operational amplifier, comprising:

• (a) a differential input stage receiving a differential input signal;
• (b) a folded cascode stage receiving first and second output signals from the differential input stage;
• (c) a rail-to-rail class AB output stage including
• i. a P-channel pull-up transistor having a source coupled to a first supply rail voltage, a gate coupled to a first input conductor of the output stage, and a drain coupled to an output terminal of the output stage, the first input conductor conducting a first current produced by the folded cascode stage,
• ii. an N-channel pull-down transistor having a source coupled to a second supply rail voltage, a gate coupled to a second input conductor of the output stage, and a drain coupled to the output terminal, the second input conductor conducting a second current produced by the folded cascode stage,
• iii. a P-channel first bias transistor having a source coupled to the first input conductor,
• iv. an N-channel second bias transistor having a source coupled to the second input terminal and a drain coupled to a drain of the first bias transistor,
• v. a P-channel third bias transistor having a source coupled to the input conductor and a drain coupled to the second input conductor,
• vi. an amplifier having an output coupled to a gate of the first bias transistor, a non-inverting input coupled to the drain of the second bias transistor, and an inverting input coupled to a first voltage source, and
• vii a second voltage source coupled to the gate of the second bias transistor.