US 6,539,490 B1 · Clock distribution without clock delay or skew

Abstract

The present invention provides a method and apparatus, for integrated circuits, that is able to generate clock signals at different destination points with little or no clock signal delay or skew. A slow rising input clock signal is propagated across a low loss transmission line. The slow rising input signal creates a region of substantially no clock signal delay between the signal at the beginning of the low loss transmission line and the signal at the end of the low loss transmission line. Comparators are used to compare the signals at the beginning and end of the low loss transmission lines and compare them to a reference signal. The compared signals are sampled during the region of substantially no clock signal delay or skew. The sampled clock signals with substantially no delay are sent to local destination points or other low loss transmission lines within the integrated circuit to transmit the signal to remote destination points.

Claims73

Dependent claims

A circuit for reducing signal skew among a plurality of output signals comprising:

a source of clock signals;
a first low loss transmission line coupled to an output of said clock signal source;
and
a first output terminal at a first end of said transmission line and a second output terminal at a second end of said transmission line;
said clock input signal source generating a clock signal having a rise rate such that signals appearing at said first and second output terminals have substantially no signal skew.

2 more elements

Dependencies are inferred from the claim text.

Clock distribution without clock delay or skew

Life of this patent

Clock distribution without clock delay or skew

Life of this patent

Abstract

Claims73