Wirebond assembly for high-speed integrated circuits
AssigneeRambus Inc.
InventorsDavid A. Secker, Nirmal Jain
Life of this patent
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Abstract
A semiconductor device assembly facilitates high-speed communication between an integrated-circuit die and external circuitry. The die is mounted on a wiring board that includes rows of bond sites in which the signal-bearing bond sites are separated by bond sites bearing DC voltage levels. Signal-bearing bond wires extending from the bond sites are thus separated from one another by bond wires at fixed voltage levels. This arrangement improves shielding between signal wires, thereby minimizing cross-talk and facilitating high data rates.
Claims27
A semiconductor device assembly comprising:
- a circuit die having a row of interior bond pads arranged along a die edge and a row of exterior bond pads arranged along the die edge between the row of interior bond pads and the die edge;
- a package substrate disposed beneath the circuit die and having a row of interior bond sites arranged along the die edge and a row of exterior bond sites arranged along the die edge and separated from the die edge by the row of interior bond sites, wherein a plurality of the interior bond sites are electrically connected to corresponding ones of the exterior bond sites;
- a first plurality of bond wires connected between ones of the exterior bond pads and corresponding ones of the interior bond sites, wherein the first plurality of bond wires includes at least four signal wires and at least four shield wires, and wherein the four signal wires of the first plurality of bond wires are separated from one another by shield wires from among the at least four shield wires of the first plurality of bond wires;
- and
- a second plurality of bond wires connected between ones of the interior bond pads and ones of the exterior bond sites electrically connected to the corresponding one of the interior bond sites, wherein the second plurality of bond wires includes at least four signal wires and at least four shield wires, and wherein the four signal wires of the second plurality of bond wires are separated from one another by shield wires from among the at least four shield wires of the second plurality of bond wires;
- wherein the four signal wires from the first plurality of bond wires extend beneath and, in at least one dimension, substantially in parallel with shield wires of the second plurality of bond wires.
A semiconductor device assembly comprising:
- a circuit die having a row of interior bond pads arranged along a die edge and a row of exterior bond pads arranged along the edge between the row of interior bond pads and the edge;
- a package substrate having a row of interior bond sites and a row of exterior bond sites, wherein a plurality of the interior bond sites are electrically connected to corresponding ones of the exterior bond sites;
- a first plurality of bond wires connected between ones of the exterior bond pads and corresponding ones of the interior bond sites;
- and
- a second plurality of bond wires connected between ones of the interior bond pads and ones of the exterior bond sites electrically connected to the corresponding one of the interior bond sites.
A bus for conveying at least eight signals in parallel between a package substrate and a circuit die, the at least eight signals divided into first and second signal subsets, the bus comprising:
- a first row of wire bonds arranged on a surface of the package substrate, the first row of wire bonds including alternating shield and signal wire bonds, the signal wire bonds in the first row adapted to convey the first subset of the at least eight signals;
- and
- a second row of wire bonds arranged on the surface of the package substrate, the second row of wire bonds including alternating shield and signal wire bonds, the signal wire bonds in the second row adapted to convey the second subset of the at least eight signals.
Dependencies are inferred from the claim text.