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US 6,534,781 B2Granted
Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact
AssigneeOvonyx, Inc.
InventorCharles Dennison
Life of this patent
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Abstract
The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode.
Claims8
An embedded phase-change memory array comprising:
- spaced apart first and second active areas that are disposed in a substrate;
- a CMOS logic structure that is peripheral to the memory array, wherein the CMOS logic structure comprises self-aligned silicide structures disposed over and above doped active areas;
- a recess comprising a bottom and walls, wherein the recess communicates to the first active area and the second active area;
- and
- a polysilicon film disposed in the recess, wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls.
2 more elements
An apparatus comprising:
- a dedicated memory chip including a plurality of first address lines and a plurality of second address lines on a substrate, addressing circuitry coupled to the plurality of first address lines and the plurality of second address lines, a plurality of memory cells formed between respective ones of the plurality of first address lines and the plurality of second address lines each memory cell including a spaced apart first active area and second active area disposed in the substrate and a recess in the substrate including a bottom and walls, a CMOS logic structure that is peripheral to the plurality of memory cells, and a polysilicon film disposed in the recess,
- wherein the polysilicon film has a first conductivity at the bottom and a second conductivity at the walls,
- wherein the CMOS logic structure includes self-aligned silicide structures disposed over and above doped active areas,
- wherein the recess communicates to the first active area and the second active area.
1 more element
Dependencies are inferred from the claim text.