US 6,532,556 B1 · Data management for multi-bit-per-cell memories

Abstract

A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Claims22

Dependent claims

A multi-bit-per-cell memory comprising:

an array of memory cells wherein each memory cell stores N bits of information;
a scrambler connected to receive a group of M data bits and provide a set of scrambled N-bit values containing bits from the group, wherein M is an integer greater than N, and bits in each scrambled N-bit value have an order that differs from an order in the group;
and
a write circuit coupled to the scrambler and the array, wherein the write circuit writes each scrambled N-bit value from the scrambler into a memory cell associated with the scrambled N-bit value.

1 more element

Dependencies are inferred from the claim text.

Data management for multi-bit-per-cell memories

Life of this patent

Data management for multi-bit-per-cell memories

Life of this patent

Abstract

Claims22