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US 6,531,754 B1Granted
Manufacturing method of partial SOI wafer, semiconductor device using the partial SOI wafer and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsHajime Nagano, Takashi Yamada, Tsutomu Sato, Ichiro Mizushima, Osamu Fujii
Life of this patent
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Abstract
A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.
Claims14
A semiconductor device comprising:
- a first semiconductor region having a buried oxide layer formed therein,
- a second semiconductor region in which the buried oxide layer does not exist,
- a trench formed to a depth to reach at least the buried oxide layer in a boundary portion between said first and second semiconductor regions, and
- an insulating layer for isolation buried in said trench,
- wherein an angle made by the bottom surface of said isolation insulating layer with the side surface of said second semiconductor region is an obtuse angle.
2 more elements
A semiconductor device comprising:
- a first semiconductor region having a buried oxide layer formed therein,
- a second semiconductor region in which the buried oxide layer does not exist,
- a trench formed to a depth to reach at least the buried oxide layer in a boundary portion between said first and second semiconductor regions, and
- an insulating layer for isolation buried in said trench,
- wherein a portion near a contact portion of the bottom surface of said isolation insulating layer with said second semiconductor region has a curved surface.
2 more elements
Dependencies are inferred from the claim text.