Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors
AssigneeNorth Carolina State University
InventorsJon-Paul Maria, Angus Ian Kingon
Life of this patent
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Abstract
Lanthanum oxide-based gate dielectrics are provided for integrated circuit field effect transistors. The gate dielectrics may include lanthanum oxide, preferably amorphous lanthanum oxide and/or an alloy of lanthanum oxide and silicon oxide, such as lanthanum silicate (La2SiO5). Lanthanum oxide-based gate dielectrics may be fabricated by evaporating lanthanum on a silicon surface of an integrated circuit substrate. The lanthanum may be evaporated in the presence of oxygen. Lanthanum and silicon may be co-evaporated. An anneal then may be performed. Lanthanum oxide-based dielectrics also may be used for integrated circuit capacitors.
Claims34
A gate dielectric for an integrated circuit field effect transistor, the gate dielectric comprising:
- an amorphous layer comprising an alloy of lanthanum oxide and silicon oxide.
A gate dielectric for an integrated circuit field effect transistor, the gate dielectric comprising:
- a first sublayer comprising (La2O3)x1(SiO2)1−x1;
- a second sublayer comprising (La2O3)x2(SiO2)1−x2 on the first sublayer, where x1≦x2;
- and
- a third sublayer comprising (La2O3)x3(SiO2)1−x3 on the second sublayer, opposite the first sublayer, where x3≦x2, and where 0<x1, x2, x3≦1.
A field effect transistor comprising:
- spaced apart source and drain regions in an integrated circuit substrate;
- and
- an insulated gate on the integrated circuit substrate, the insulated gate comprising a gate dielectric amorphous layer comprising an alloy of lanthanum oxide and silicon oxide on the integrated circuit substrate and a gate electrode on the gate dielectric amorphous layer comprising an alloy of lanthanum oxide and silicon oxide, opposite the integrated circuit.
A field effect transistor comprising:
- spaced apart source and drain regions in an integrated circuit substrate;
- and
- an insulated gate on the integrated circuit substrate, the insulated gate comprising a gate dielectric layer comprising an alloy of lanthanum oxide and silicon oxide on the integrated circuit substrate and a gate electrode on the gate dielectric layer comprising an alloy of lanthanum oxide and silicon oxide, opposite the integrated circuit;
- wherein the gate dielectric layer comprising (La2O3)x(SiO2)1−x comprises:
- a first sublayer comprising (La2O3)x1(SiO2)1−x1, adjacent the integrated circuit substrate;
- a second sublayer comprising (La2O3)x2(SiO2)1−x2, on the first sublayer opposite the integrated circuit substrate, where x1≦x2;
- and
- a third sublayer comprising (La2O3)x3(SiO2)1−x3 on the second sublayer, opposite the first sublayer, where x3≦x2, and where 0<x1, x2, x3≦1.
An integrated circuit complementary field effect transistor pair comprising:
- an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor in an integrated circuit substrate, each of which comprises an insulated gate including a gate dielectric amorphous layer comprising an alloy of lanthanum oxide and silicon oxide on the integrated circuit substrate and a gate electrode on the gate dielectric layer comprising an alloy of lanthanum oxide and silicon oxide, opposite the integrated circuit substrate.
An integrated circuit complementary field effect transistor pair comprising:
- an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor in an integrated circuit substrate, each of which comprises an insulated gate including a gate dielectric layer comprising an alloy of lanthanum oxide and silicon oxide on the integrated circuit substrate and a gate electrode on the gate dielectric layer comprising an alloy of lanthanum oxide and silicon oxide, opposite the integrated circuit substrate;
- wherein the gate dielectric layer comprising (La2O3)x(SiO2)1−x comprises:
- a first sublayer comprising (La2O3)x1(SiO2)1−x1;
- a second sublayer comprising (La2O3)x2(SiO2)1−x2 on the first sublayer, where x1≦x2;
- and
- a third sublayer comprising (La2O3)x3(SiO2)1−x3 on the second sublayer, opposite the first sublayer, where x3≦x2, and where 0<x1, x2, x3≦1.
Dependencies are inferred from the claim text.