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AssigneesLattice Semiconductor Corporation, U. of Kentucky, Research Foundation
InventorsMiron Abramovici, Charles E. Stroud, John M. Emmert
Estimating the term…
A method of fault tolerant operation of field programmable gate arrays (FPGAs) utilizing incremental reconfiguration during normal on-line operation includes configuring an FPGA into initial self-testing areas and a working area. Within the self-testing areas, programmable logic blocks (PLBs) of the FPGA are tested for faults. Upon the detection of one or more faults within the PLBs, the faulty PLBs are isolated and their modes of operation exhaustively tested. Partially faulty PLBs are allowed to continue operation in a diminished capacity as long as the faulty modes of operation do not prevent the PLBs from performing non-faulty system functions. After testing the programmable logic blocks in the initial self-testing areas, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and at least a portion of the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA repeating the steps of testing and reconfiguring until the entire FPGA has undergone testing, or continuously. Prior to relocating the initial self-testing areas, the initial self-testing areas are reconfigured to replace unusable faulty PLBs with spare PLBs. Spare PLBs are initially allocated throughout the working area. Specifically, each operational PLB within the working area is allocated an adjacent preferred spare PLB. Predetermined configurations of the FPGA utilizing the preferred spares are used to avoid the faulty PLBs. If the initially allocated spares are incapable of utilization, then a subsequent portion of the PLBs within the working area are allocated as spares and new replacement configurations determined. As the number of spare PLBs is diminished over time, additional spare PLBs are at some point necessarily removed from the self-testing areas. In this manner, the testing and roving capabilities of the self-testing area are also inevitably diminished. Eventually, roving, testing, and even operation of the FPGA will cease.
A method of fault tolerant operation of a field programmable gate array utilizing incremental reconfiguration during normal on-line operation comprising the steps of:
A method of fault tolerant operation of a field programmable gate array utilizing incremental reconfiguration during normal on-line operation comprising the steps of:
A method of fault tolerant on-line operation of a field programmable gate array utilizing incremental reconfiguration comprising the steps of:
An apparatus for testing programmable logic blocks of a field programmable gate array and supporting fault tolerant on-line operation of the field programmable gate array utilizing incremental reconfiguration comprising:
A field programmable gate array comprising:
Dependencies are inferred from the claim text.