Apparatus and method for testing rambus DRAMs
AssigneeMicron Technology, Inc.
InventorsChristopher B. Cooper, Siang Tian Giam, Jerry D. McBride, Scott L. Ayres
Life of this patent
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Abstract
An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.
Claims28
A method of testing a computer memory device which is on a semiconductor wafer comprising:
- precharging a bank of locations of the computer memory device at a time defined by a first portion of a first control signal;
- latching the bank of locations at a time defined by a second portion of said first control signal;
- selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- selecting a column address and a bank address at a time defined by a portion of a third control signal;
- reading data from the computer memory device that is stored at the location defined by the selected row column and bank addresses;
- and
- comparing data read from the location with test data so as to test the integrity of the memory device.
A method of testing a computer memory device which is on a semiconductor wafer comprising:
- precharging a bank of locations of the computer memory device at a time defined by a leading edge of a first control signal;
- latching the bank of locations at a time defined by a trailing edge of said first control signal;
- selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- selecting a column address and a bank address at a time defined by a portion of a third control signal;
- reading data from the computer memory device that is stored at the location defined by the selected row, column and bank addresses;
- and
- comparing data read from the location with test data so as to test the integrity of the memory device.
A method of testing a computer memory device which is on a semiconductor wafer comprising:
- dividing the computer memory device into a plurality of array cores, wherein each said array core comprises an independent repair region;
- precharging a bank of locations in at least one of the array cores at a time defined by a first portion of a first control signal;
- latching the bank of locations at a time defined by a second portion of said first control signal;
- selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- selecting a column address and the a address at a time defined by a portion of a third control signal;
- reading data from the computer memory device that is stored at the location in at least one array core defined by the selected row, column and bank addresses;
- compressing the data read from each array core so as to define a single data bit that is used to test each array core;
- and
- comparing data read from the location with test data so as to test the integrity of the memory device.
A method of testing a computer memory device which is on a semiconductor wafer comprising:
- precharging a bank of locations of the computer memory device at a time defined by a first portion of a first control signal;
- latching the bank of locations at a time defined by a second portion of said first control signal;
- selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- selecting a column address and a bank address at a time defined by a portion of a third control signal;
- writing data to the computer memory device at the location defined by the selected row, column and bank addresses;
- reading data from the computer memory device that is stored at the location defined by the selected row, column and bank addresses;
- and
- comparing data read from the location with test data so as to test the integrity of the memory device.
An apparatus for testing a computer memory device which is on a semiconductor wafer comprising:
- means for precharging a bank of locations of the computer memory device at a time defined by a first portion of a first control signal;
- means for latching the bank of locations at a time defined by a second portion of said first control signal;
- means for selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- means for selecting a column address and a bank address at a time defined by a portion of a third control signal;
- means for reading data from the computer memory device that is stored at the location defined by the selected row, column and bank addresses;
- and
- means for comparing data read from the location with test data so as to test the integrity of the memory device.
An apparatus for testing a computer memory device which is on a semiconductor wafer by comprising:
- means for dividing the computer memory device into a plurality of array cores, wherein each said array core comprises an independent repair region;
- means for precharging a bank of locations in at least one of the array cores at a time defined by a first portion of a first control signal;
- means for latching the bank of locations at a time defined by a second portion of said first control signal;
- means for selecting a row address in the bank of locations at a time defined by a portion of a second control signal;
- means for selecting a column address and a bank address at a time defined by a portion of a third control signal;
- means for reading data from the computer memory device that is stored at the location in at least one array core defined by the selected row, column and bank addresses;
- means for compressing data read from each array core so as to define a single data bit that is used to test each array core;
- and
- means for comparing data read from the location with test data so as to test the integrity of the memory device.
Dependencies are inferred from the claim text.